diff --git a/riscv-tools b/riscv-tools
index 116e2f99..cc599fce 160000
--- a/riscv-tools
+++ b/riscv-tools
@@ -1 +1 @@
-Subproject commit 116e2f99b5d6b2174a89e69672049230a3bdc5f9
+Subproject commit cc599fce1ad7f0823c032f7c8dde0c0c363bad7d
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 4cf98468..d258113b 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -258,7 +258,7 @@ class Top extends Module {
   val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
   val rc = RocketConfiguration(tl, ic, dc,
                                fpu = HAS_FPU
-                               //,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
+                               ,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
                               )
 
   val io = new VLSITopIO(HTIF_WIDTH)