From 8a47c3f346c82a13bfa685639bd52b6b07137414 Mon Sep 17 00:00:00 2001
From: Eric Love <ericlove@berkeley.edu>
Date: Fri, 11 Mar 2016 16:54:56 -0800
Subject: [PATCH] Make sure there's enough xact id bits

---
 uncore/src/main/scala/rtc.scala | 1 +
 1 file changed, 1 insertion(+)

diff --git a/uncore/src/main/scala/rtc.scala b/uncore/src/main/scala/rtc.scala
index 6c3f83a4..f22121a9 100644
--- a/uncore/src/main/scala/rtc.scala
+++ b/uncore/src/main/scala/rtc.scala
@@ -51,6 +51,7 @@ class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule
     id = coreId,
     addr = addrTable(coreId),
     size = UInt(log2Up(csrDataBytes)))
+  require(p(MIFMasterTagBits) >= log2Up(nCores))
 
   io.w.valid := sending_data
   io.w.bits := NastiWriteDataChannel(data = rtc)