riscv/rocket-chip
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Add new RTC as TileLink slave, not AXI master

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This commit is contained in:
Andrew Waterman 2016-04-27 11:55:35 -07:00
parent eb0b5ec61e
commit 87cecc336f
2 changed files with 33 additions and 46 deletions
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1
uncore/src/main/scala/htif.scala
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@ -44,6 +44,7 @@ class HostIO(w: Int) extends Bundle {
class HtifIO(implicit p: Parameters) extends HtifBundle()(p) { class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
val reset = Bool(INPUT) val reset = Bool(INPUT)
val id = UInt(INPUT, log2Up(nCores)) val id = UInt(INPUT, log2Up(nCores))
val timerIRQ = Bool(INPUT)
val csr = new SmiIO(csrDataBits, 12).flip val csr = new SmiIO(csrDataBits, 12).flip
} }

84
uncore/src/main/scala/rtc.scala
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@ -6,59 +6,45 @@ import cde.{Parameters, Field}
case object RTCPeriod extends Field[Int] case object RTCPeriod extends Field[Int]
class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule class RTC(nHarts: Int)(implicit val p: Parameters) extends Module
with HasTileLinkParameters with HasTileLinkParameters
with HasAddrMapParameters { with HasAddrMapParameters {
val io = new ClientUncachedTileLinkIO val io = new Bundle {
val tl = new ClientUncachedTileLinkIO().flip
val addrTable = Vec.tabulate(nCores) { i => val irqs = Vec(nHarts, Bool()).asOutput
UInt(addrMap(s"conf:csr$i").start + csr_MTIME * csrDataBytes, p(PAddrBits))
} }
val rtc = Reg(init=UInt(0, csrDataBits)) val w = 64
val rtc_tick = Counter(p(RTCPeriod)).inc() val regs = Reg(Vec(nHarts+1, UInt(width = w)))
require(w == tlDataBits) // TODO relax this constraint for narrower TL
val sending = Reg(init = Bool(false)) val acq = Queue(io.tl.acquire, 1)
val send_acked = Reg(init = Vec.fill(nCores)(Bool(true)))
val coreId = Wire(UInt(width = log2Up(nCores)))
when (rtc_tick) { val full_addr = acq.bits.full_addr()
rtc := rtc + UInt(1) val byte_addr = full_addr(log2Up(w/8)-1,0)
send_acked := Vec.fill(nCores)(Bool(false)) val size = w/8*(nHarts+1)
sending := Bool(true) val addr = full_addr(log2Up(size)-1,log2Up(w/8))
} val rdata = regs(addr)
val wdata = acq.bits.data
if (nCores > 1) { val read = acq.bits.a_type === Acquire.getType
val (send_cnt, send_done) = Counter(io.acquire.fire(), nCores) val write = acq.bits.a_type === Acquire.putType
val wmask = acq.bits.full_wmask()
when (send_done) { sending := Bool(false) } assert(!acq.valid || read || write, "unsupported RTC operation")
coreId := send_cnt io.tl.grant.valid := acq.valid
} else { acq.ready := io.tl.grant.ready
when (io.acquire.fire()) { sending := Bool(false) } io.tl.grant.bits := Grant(
is_builtin_type = Bool(true),
coreId := UInt(0) g_type = acq.bits.getBuiltInGrantType(),
} client_xact_id = acq.bits.client_xact_id,
manager_xact_id = UInt(0),
when (io.grant.fire()) { send_acked(io.grant.bits.client_xact_id) := Bool(true) } addr_beat = UInt(0),
data = rdata)
val addr_full = addrTable(coreId)
val addr_block = addr_full(p(PAddrBits) - 1, p(CacheBlockOffsetBits)) for ((irq, cmp) <- io.irqs zip regs.tail)
val addr_beat = addr_full(p(CacheBlockOffsetBits) - 1, tlByteAddrBits) irq := (regs(0) >= cmp)
val addr_byte = addr_full(tlByteAddrBits - 1, 0)
val wmask = Fill(csrDataBytes, UInt(1, 1)) << addr_byte when (Counter(p(RTCPeriod)).inc()) { regs(0) := regs(0) + UInt(1) }
when (acq.valid && write) { regs(addr) := wdata & wmask | rdata & ~wmask }
io.acquire.valid := sending when (reset) { regs(0) := UInt(0) }
io.acquire.bits := Put(
client_xact_id = coreId,
addr_block = addr_block,
addr_beat = addr_beat,
wmask = wmask,
data = Fill(tlDataBytes / csrDataBytes, rtc))
io.grant.ready := Bool(true)
require(tlClientXactIdBits >= log2Up(nCores))
assert(!rtc_tick || send_acked.reduce(_ && _),
"Not all clocks were updated for rtc tick")
} }