riscv/rocket-chip
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Pass TLB flush signal to I$ explicitly

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This commit is contained in:
Andrew Waterman
2016-04-22 15:20:17 -07:00
parent b7527268bb
commit 84fd45fd77
2 changed files with 6 additions and 4 deletions
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3
rocket/src/main/scala/rocket.scala
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@ -496,7 +496,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret
Mux(replay_wb, wb_reg_pc, // replay
mem_npc)).toUInt // mispredicted branch
io.imem.invalidate := wb_reg_valid && wb_ctrl.fence_i
io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i
io.imem.flush_tlb := csr.io.fatc
io.imem.resp.ready := !ctrl_stalld || csr.io.interrupt
io.imem.btb_update.valid := mem_reg_valid && !mem_npc_misaligned && mem_wrong_npc && mem_cfi_taken && !take_pc_wb