diff --git a/rocket/src/main/scala/frontend.scala b/rocket/src/main/scala/frontend.scala
index 602b13e0..490ae71c 100644
--- a/rocket/src/main/scala/frontend.scala
+++ b/rocket/src/main/scala/frontend.scala
@@ -23,7 +23,8 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
   val btb_update = Valid(new BTBUpdate)
   val bht_update = Valid(new BHTUpdate)
   val ras_update = Valid(new RASUpdate)
-  val invalidate = Bool(OUTPUT)
+  val flush_icache = Bool(OUTPUT)
+  val flush_tlb = Bool(OUTPUT)
   val npc = UInt(INPUT, width = vaddrBitsExtended)
 }
 
@@ -80,7 +81,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
     btb.io.btb_update := io.cpu.btb_update
     btb.io.bht_update := io.cpu.bht_update
     btb.io.ras_update := io.cpu.ras_update
-    btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate
+    btb.io.invalidate := io.cpu.flush_icache || io.cpu.flush_tlb // virtual tags
     when (!stall && !icmiss) {
       btb.io.req.valid := true
       s2_btb_resp_valid := btb.io.resp.valid
@@ -103,7 +104,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
   io.mem <> icache.io.mem
   icache.io.req.valid := !stall && !s0_same_block
   icache.io.req.bits.idx := io.cpu.npc
-  icache.io.invalidate := io.cpu.invalidate
+  icache.io.invalidate := io.cpu.flush_icache
   icache.io.s1_ppn := tlb.io.resp.ppn
   icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.ptw.invalidate
 
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index b4b9601a..45bf48a8 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -496,7 +496,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
     Mux(wb_xcpt || csr.io.eret, csr.io.evec,     // exception or [m|s]ret
     Mux(replay_wb,              wb_reg_pc,       // replay
                                 mem_npc)).toUInt // mispredicted branch
-  io.imem.invalidate := wb_reg_valid && wb_ctrl.fence_i
+  io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i
+  io.imem.flush_tlb := csr.io.fatc
   io.imem.resp.ready := !ctrl_stalld || csr.io.interrupt
 
   io.imem.btb_update.valid := mem_reg_valid && !mem_npc_misaligned && mem_wrong_npc && mem_cfi_taken && !take_pc_wb