coreplex => subsystem

src/main/scala/tile/BaseTile.scala

@@ -5,7 +5,7 @@ package freechips.rocketchip.tile
 import Chisel._
 
 import freechips.rocketchip.config._
-import freechips.rocketchip.coreplex._
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.rocket._
@@ -122,7 +122,7 @@ trait HasTileParameters {
 }
 
 /** Base class for all Tiles that use TileLink */
-abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCrossing)
+abstract class BaseTile(tileParams: TileParams, val crossing: SubsystemClockCrossing)
                        (implicit p: Parameters) extends LazyModule with HasTileParameters with HasCrossing
 {
   def module: BaseTileModuleImp[BaseTile]

src/main/scala/tile/Interrupts.scala

@@ -18,7 +18,7 @@ class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
   val lip = Vec(coreParams.nLocalInterrupts, Bool())
 }
 
-// Use diplomatic interrupts to external interrupts from the coreplex into the tile
+// Use diplomatic interrupts to external interrupts from the subsystem into the tile
 trait HasExternalInterrupts { this: BaseTile =>
 
   val intInwardNode = intXbar.intnode
@@ -50,7 +50,7 @@ trait HasExternalInterrupts { this: BaseTile =>
 
   // TODO: the order of the following two functions must match, and
   //         also match the order which things are connected to the
-  //         per-tile crossbar in coreplex.HasRocketTiles
+  //         per-tile crossbar in subsystem.HasRocketTiles
 
   // debug, msip, mtip, meip, seip, lip offsets in CSRs
   def csrIntMap: List[Int] = {

src/main/scala/tile/L1Cache.scala

@@ -5,7 +5,7 @@ package freechips.rocketchip.tile
 import Chisel._
 
 import freechips.rocketchip.config.{Parameters, Field}
-import freechips.rocketchip.coreplex.CacheBlockBytes
+import freechips.rocketchip.subsystem.CacheBlockBytes
 import freechips.rocketchip.tilelink.ClientMetadata
 import freechips.rocketchip.util._
 

src/main/scala/tile/LazyRoCC.scala

@@ -6,7 +6,7 @@ package freechips.rocketchip.tile
 import Chisel._
 
 import freechips.rocketchip.config._
-import freechips.rocketchip.coreplex._
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.tilelink._

src/main/scala/tile/RocketTile.scala

@@ -5,7 +5,7 @@ package freechips.rocketchip.tile
 
 import Chisel._
 import freechips.rocketchip.config._
-import freechips.rocketchip.coreplex.CoreplexClockCrossing
+import freechips.rocketchip.subsystem.SubsystemClockCrossing
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
@@ -33,7 +33,7 @@ case class RocketTileParams(
 
 class RocketTile(
     val rocketParams: RocketTileParams,
-    crossing: CoreplexClockCrossing)
+    crossing: SubsystemClockCrossing)
   (implicit p: Parameters) extends BaseTile(rocketParams, crossing)(p)
     with HasExternalInterrupts
     with HasLazyRoCC  // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache