78 lines
2.3 KiB
Scala
78 lines
2.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tile
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
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val debug = Bool()
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val mtip = Bool()
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val msip = Bool()
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val meip = Bool()
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val seip = usingVM.option(Bool())
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val lip = Vec(coreParams.nLocalInterrupts, Bool())
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}
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// Use diplomatic interrupts to external interrupts from the subsystem into the tile
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trait HasExternalInterrupts { this: BaseTile =>
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val intInwardNode = intXbar.intnode
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protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
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intSinkNode := intXbar.intnode
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val intcDevice = new Device {
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def describe(resources: ResourceBindings): Description = {
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Description(s"cpus/cpu@$hartId/interrupt-controller", Map(
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"compatible" -> "riscv,cpu-intc".asProperty,
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"interrupt-controller" -> Nil,
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"#interrupt-cells" -> 1.asProperty))
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}
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}
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ResourceBinding {
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Resource(intcDevice, "reg").bind(ResourceInt(BigInt(hartId)))
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intSinkNode.edges.in.flatMap(_.source.sources).map { case s =>
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for (i <- s.range.start until s.range.end) {
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csrIntMap.lift(i).foreach { j =>
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s.resources.foreach { r =>
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r.bind(intcDevice, ResourceInt(j))
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}
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}
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}
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}
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}
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// TODO: the order of the following two functions must match, and
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// also match the order which things are connected to the
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// per-tile crossbar in subsystem.HasRocketTiles
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// debug, msip, mtip, meip, seip, lip offsets in CSRs
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def csrIntMap: List[Int] = {
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val nlips = tileParams.core.nLocalInterrupts
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val seip = if (usingVM) Seq(9) else Nil
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List(65535, 3, 7, 11) ++ seip ++ List.tabulate(nlips)(_ + 16)
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}
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// go from flat diplomatic Interrupts to bundled TileInterrupts
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def decodeCoreInterrupts(core: TileInterrupts) {
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val async_ips = Seq(core.debug)
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val periph_ips = Seq(
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core.msip,
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core.mtip,
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core.meip)
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val seip = if (core.seip.isDefined) Seq(core.seip.get) else Nil
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val core_ips = core.lip
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val (interrupts, _) = intSinkNode.in(0)
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(async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i }
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}
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}
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