47 lines
1.4 KiB
Scala
47 lines
1.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tile
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import Chisel._
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.subsystem.CacheBlockBytes
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import freechips.rocketchip.tilelink.ClientMetadata
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import freechips.rocketchip.util._
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trait L1CacheParams {
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def nSets: Int
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def nWays: Int
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def rowBits: Int
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def nTLBEntries: Int
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def blockBytes: Int // TODO this is ignored in favor of p(CacheBlockBytes) in BaseTile
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}
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trait HasL1CacheParameters extends HasTileParameters {
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val cacheParams: L1CacheParams
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private val bundleParams = p(SharedMemoryTLEdge).bundle
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def nSets = cacheParams.nSets
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def blockOffBits = lgCacheBlockBytes
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def idxBits = log2Up(cacheParams.nSets)
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def untagBits = blockOffBits + idxBits
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def tagBits = bundleParams.addressBits - untagBits
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def nWays = cacheParams.nWays
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def wayBits = log2Up(nWays)
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def isDM = nWays == 1
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def rowBits = cacheParams.rowBits
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def rowBytes = rowBits/8
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def rowOffBits = log2Up(rowBytes)
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def nTLBEntries = cacheParams.nTLBEntries
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def cacheDataBits = bundleParams.dataBits
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def cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits
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def refillCycles = cacheDataBeats
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}
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abstract class L1CacheModule(implicit val p: Parameters) extends Module
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with HasL1CacheParameters
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abstract class L1CacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasL1CacheParameters
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