diff --git a/groundtest/src/main/scala/unittests/AtosConverterTest.scala b/groundtest/src/main/scala/unittests/AtosConverterTest.scala
deleted file mode 100644
index 62f1deec..00000000
--- a/groundtest/src/main/scala/unittests/AtosConverterTest.scala
+++ /dev/null
@@ -1,127 +0,0 @@
-package groundtest.unittests
-
-import Chisel._
-import junctions._
-import junctions.NastiConstants._
-import cde.Parameters
-
-class AtosConverterTestFrontend(implicit p: Parameters) extends NastiModule()(p) {
-  val io = new Bundle {
-    val nasti = new NastiIO
-    val finished = Bool(OUTPUT)
-  }
-
-  val n_words = 4
-  val test_data = Vec.tabulate(n_words) { i => UInt(i * 48) }
-
-  val (s_idle :: s_waddr :: s_wdata :: s_wresp ::
-       s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 7)
-  val state = Reg(init = s_idle)
-
-  when (state === s_idle) { state := s_waddr }
-  when (io.nasti.aw.fire()) { state := s_wdata }
-  when (io.nasti.w.fire() && io.nasti.w.bits.last) { state := s_wresp }
-  when (io.nasti.b.fire()) { state := s_raddr }
-  when (io.nasti.ar.fire()) { state := s_rresp }
-  when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
-
-  val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
-
-  io.nasti.aw.valid := (state === s_waddr)
-  io.nasti.aw.bits := NastiWriteAddressChannel(
-    id = UInt(0),
-    addr = UInt(0),
-    size = UInt(log2Up(nastiXDataBits / 8)),
-    len = UInt(n_words - 1))
-
-  io.nasti.w.valid := (state === s_wdata)
-  io.nasti.w.bits := NastiWriteDataChannel(
-    data = test_data(w_count),
-    last = w_count === UInt(n_words - 1))
-
-  io.nasti.ar.valid := (state === s_raddr)
-  io.nasti.ar.bits := NastiReadAddressChannel(
-    id = UInt(0),
-    addr = UInt(0),
-    size = UInt(log2Up(nastiXDataBits / 8)),
-    len = UInt(n_words - 1))
-
-  io.nasti.b.ready := (state === s_wresp)
-  io.nasti.r.ready := (state === s_rresp)
-
-  io.finished := (state === s_done)
-
-  val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
-
-  assert(!io.nasti.r.valid || io.nasti.r.bits.data === test_data(r_count),
-    "AtosConverterTest: returned data doesn't match expected")
-}
-
-class AtosConverterTestBackend(implicit p: Parameters) extends NastiModule()(p) {
-  val io = new Bundle {
-    val nasti = (new NastiIO).flip
-    val finished = Bool(OUTPUT)
-  }
-
-  val (s_waddr :: s_wdata :: s_wresp ::
-       s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 6)
-  val state = Reg(init = s_waddr)
-
-  val n_words = 4
-  val test_data = Reg(Vec(n_words, UInt(width = nastiXDataBits)))
-  val req_id = Reg(UInt(width = nastiXIdBits))
-
-  val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
-  val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
-
-  when (io.nasti.aw.fire()) {
-    req_id := io.nasti.aw.bits.id
-    state := s_wdata
-  }
-  when (io.nasti.w.fire()) {
-    test_data(w_count) := io.nasti.w.bits.data
-    when (io.nasti.w.bits.last) { state := s_wresp }
-  }
-  when (io.nasti.b.fire()) { state := s_raddr }
-  when (io.nasti.ar.fire()) {
-    req_id := io.nasti.ar.bits.id
-    state := s_rresp
-  }
-  when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
-
-  io.nasti.aw.ready := (state === s_waddr)
-  io.nasti.w.ready := (state === s_wdata)
-  io.nasti.ar.ready := (state === s_raddr)
-
-  io.nasti.b.valid := (state === s_wresp)
-  io.nasti.b.bits := NastiWriteResponseChannel(id = req_id)
-
-  io.nasti.r.valid := (state === s_rresp)
-  io.nasti.r.bits := NastiReadDataChannel(
-    id = req_id,
-    data = test_data(r_count),
-    last = r_last)
-
-  io.finished := (state === s_done)
-}
-
-class AtosConverterTest(implicit p: Parameters) extends UnitTest {
-  val frontend = Module(new AtosConverterTestFrontend)
-  val backend = Module(new AtosConverterTestBackend)
-
-  val serdes = Module(new AtosSerdes(8))
-  val desser = Module(new AtosDesser(8))
-
-  val client_conv = Module(new AtosClientConverter)
-  val manager_conv = Module(new AtosManagerConverter)
-
-  client_conv.io.nasti <> frontend.io.nasti
-  serdes.io.wide <> client_conv.io.atos
-  desser.io.narrow <> serdes.io.narrow
-  manager_conv.io.atos <> desser.io.wide
-  backend.io.nasti <> manager_conv.io.nasti
-
-  io.finished := frontend.io.finished && backend.io.finished
-}
-
-
diff --git a/groundtest/src/main/scala/unittests/BRAMSlaveTest.scala b/groundtest/src/main/scala/unittests/BRAMSlaveTest.scala
deleted file mode 100644
index 4104c922..00000000
--- a/groundtest/src/main/scala/unittests/BRAMSlaveTest.scala
+++ /dev/null
@@ -1,82 +0,0 @@
-package groundtest.unittests
-
-import Chisel._
-import uncore.tilelink._
-import uncore.devices._
-import cde.Parameters
-
-class BRAMSlaveDriver(implicit val p: Parameters) extends Module
-    with HasTileLinkParameters {
-  val io = new Bundle {
-    val mem = new ClientUncachedTileLinkIO
-    val start = Bool(INPUT)
-    val finished = Bool(OUTPUT)
-  }
-
-  val (s_idle :: s_pf_req :: s_pf_stall :: s_pf_resp ::
-       s_put_req :: s_put_stall :: s_put_resp ::
-       s_get_req :: s_get_stall :: s_get_resp ::
-       s_done :: Nil) = Enum(Bits(), 11)
-  val state = Reg(init = s_idle)
-
-  val pf_acquire = PutPrefetch(
-    client_xact_id = UInt(0),
-    addr_block = UInt(0))
-
-  val (put_beat, put_done) = Counter(
-    state === s_put_req && io.mem.acquire.ready, tlDataBeats)
-  val put_data = Fill(tlDataBits / tlBeatAddrBits, put_beat)
-
-  val put_acquire = PutBlock(
-    client_xact_id = UInt(0),
-    addr_block = UInt(0),
-    addr_beat = put_beat,
-    data = put_data)
-
-  val get_acquire = GetBlock(
-    client_xact_id = UInt(0),
-    addr_block = UInt(0))
-
-  val (get_beat, get_done) = Counter(
-    state === s_get_resp && io.mem.grant.valid, tlDataBeats)
-  val get_data = Fill(tlDataBits / tlBeatAddrBits, get_beat)
-
-  val (stall_cnt, stall_done) = Counter(
-    state === s_pf_stall || state === s_put_stall || state === s_get_stall, 4)
-
-  io.mem.acquire.valid := (state === s_pf_req) || (state === s_put_req) || (state === s_get_req)
-  io.mem.acquire.bits := MuxLookup(state, get_acquire, Seq(
-    s_pf_req -> pf_acquire,
-    s_put_req -> put_acquire))
-  io.mem.grant.ready := (state === s_pf_resp) || (state === s_put_resp) || (state === s_get_resp)
-
-  when (state === s_idle && io.start) { state := s_pf_req }
-  when (state === s_pf_req && io.mem.acquire.ready) { state := s_pf_stall }
-  when (state === s_pf_stall && stall_done) { state := s_pf_resp }
-  when (state === s_pf_resp && io.mem.grant.valid) { state := s_put_req }
-  when (state === s_put_req && io.mem.acquire.ready) { state := s_put_stall }
-  when (state === s_put_stall && stall_done) { state := s_put_req }
-  when (put_done) { state := s_put_resp }
-  when (state === s_put_resp && io.mem.grant.valid) { state := s_get_req }
-  when (state === s_get_req && io.mem.acquire.ready) { state := s_get_stall }
-  when (state === s_get_stall && stall_done) { state := s_get_resp }
-  when (state === s_get_resp && io.mem.grant.valid) { state := s_get_stall }
-  when (get_done) { state := s_done }
-
-  io.finished := (state === s_done)
-
-  assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
-         io.mem.grant.bits.data === get_data,
-         "BRAMSlaveTest: data doesn't match")
-}
-
-class BRAMSlaveTest(implicit val p: Parameters) extends UnitTest
-    with HasTileLinkParameters {
-  val driver = Module(new BRAMSlaveDriver)
-  val bram = Module(new BRAMSlave(tlDataBeats))
-  driver.io.start := io.start
-  io.finished := driver.io.finished
-  bram.io <> driver.io.mem
-}
-
-
diff --git a/groundtest/src/main/scala/unittests/Misc.scala b/groundtest/src/main/scala/unittests/Nasti.scala
similarity index 61%
rename from groundtest/src/main/scala/unittests/Misc.scala
rename to groundtest/src/main/scala/unittests/Nasti.scala
index 86d59e8f..c668fb9d 100644
--- a/groundtest/src/main/scala/unittests/Misc.scala
+++ b/groundtest/src/main/scala/unittests/Nasti.scala
@@ -2,11 +2,58 @@ package groundtest.unittests
 
 import Chisel._
 import junctions._
-import uncore.devices._
-import uncore.tilelink._
+import junctions.NastiConstants._
 import groundtest.common._
 import cde.Parameters
 
+class AtosConverterTestBackend(implicit p: Parameters) extends NastiModule()(p) {
+  val io = new Bundle {
+    val nasti = (new NastiIO).flip
+    val finished = Bool(OUTPUT)
+  }
+
+  val (s_waddr :: s_wdata :: s_wresp ::
+       s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 6)
+  val state = Reg(init = s_waddr)
+
+  val n_words = 4
+  val test_data = Reg(Vec(n_words, UInt(width = nastiXDataBits)))
+  val req_id = Reg(UInt(width = nastiXIdBits))
+
+  val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
+  val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
+
+  when (io.nasti.aw.fire()) {
+    req_id := io.nasti.aw.bits.id
+    state := s_wdata
+  }
+  when (io.nasti.w.fire()) {
+    test_data(w_count) := io.nasti.w.bits.data
+    when (io.nasti.w.bits.last) { state := s_wresp }
+  }
+  when (io.nasti.b.fire()) { state := s_raddr }
+  when (io.nasti.ar.fire()) {
+    req_id := io.nasti.ar.bits.id
+    state := s_rresp
+  }
+  when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
+
+  io.nasti.aw.ready := (state === s_waddr)
+  io.nasti.w.ready := (state === s_wdata)
+  io.nasti.ar.ready := (state === s_raddr)
+
+  io.nasti.b.valid := (state === s_wresp)
+  io.nasti.b.bits := NastiWriteResponseChannel(id = req_id)
+
+  io.nasti.r.valid := (state === s_rresp)
+  io.nasti.r.bits := NastiReadDataChannel(
+    id = req_id,
+    data = test_data(r_count),
+    last = r_last)
+
+  io.finished := (state === s_done)
+}
+
 class NastiDriver(dataWidth: Int, burstLen: Int, nBursts: Int)
     (implicit p: Parameters) extends NastiModule {
   val io = new Bundle {
@@ -98,39 +145,24 @@ class HastiTest(implicit p: Parameters) extends UnitTest {
   driver.io.start := io.start
 }
 
-class ROMSlaveTest(implicit p: Parameters) extends UnitTest {
-  val romdata = Seq(
-    BigInt("01234567deadbeef", 16),
-    BigInt("ab32fee8d00dfeed", 16))
-  val rombytes = romdata.map(_.toByteArray.reverse).flatten
-  val rom = Module(new ROMSlave(rombytes))
-  val driver = Module(new DriverSet(
-    (driverParams: Parameters) => {
-      implicit val p = driverParams
-      Seq(
-        Module(new GetMultiWidthDriver),
-        Module(new GetSweepDriver(romdata)),
-        Module(new GetBlockSweepDriver(romdata)))
-    }))
-  rom.io <> driver.io.mem
-  driver.io.start := io.start
-  io.finished := driver.io.finished
+class AtosConverterTest(implicit val p: Parameters) extends UnitTest
+    with HasNastiParameters {
+  val frontend = Module(new NastiDriver(nastiXDataBits, 4, 1))
+  val backend = Module(new AtosConverterTestBackend)
+
+  val serdes = Module(new AtosSerdes(8))
+  val desser = Module(new AtosDesser(8))
+
+  val client_conv = Module(new AtosClientConverter)
+  val manager_conv = Module(new AtosManagerConverter)
+
+  client_conv.io.nasti <> frontend.io.nasti
+  serdes.io.wide <> client_conv.io.atos
+  desser.io.narrow <> serdes.io.narrow
+  manager_conv.io.atos <> desser.io.wide
+  backend.io.nasti <> manager_conv.io.nasti
+
+  io.finished := frontend.io.finished && backend.io.finished
 }
 
-class TileLinkRAMTest(implicit val p: Parameters)
-    extends UnitTest with HasTileLinkParameters {
 
-  val depth = 2 * tlDataBeats
-  val ram = Module(new TileLinkTestRAM(depth))
-  val driver = Module(new DriverSet(
-    (driverParams: Parameters) => {
-      implicit val p = driverParams
-      Seq(
-        Module(new PutSweepDriver(depth)),
-        Module(new PutMaskDriver),
-        Module(new PutBlockSweepDriver(depth / tlDataBeats)))
-    }))
-  ram.io <> driver.io.mem
-  driver.io.start := io.start
-  io.finished := driver.io.finished
-}
diff --git a/groundtest/src/main/scala/unittests/SmiConverterTest.scala b/groundtest/src/main/scala/unittests/SmiConverterTest.scala
deleted file mode 100644
index 060b546f..00000000
--- a/groundtest/src/main/scala/unittests/SmiConverterTest.scala
+++ /dev/null
@@ -1,89 +0,0 @@
-package groundtest.unittests
-
-import Chisel._
-import junctions._
-import uncore.tilelink._
-import uncore.converters._
-import uncore.constants._
-import cde.Parameters
-
-class SmiConverterTestDriver(implicit p: Parameters) extends Module {
-  val io = new Bundle {
-    val mem = new ClientUncachedTileLinkIO
-    val start = Bool(INPUT)
-    val finished = Bool(OUTPUT)
-  }
-
-  val nChecks = 32
-  val count = Reg(init = UInt(0, log2Up(nChecks)))
-  val addr = Cat(count, UInt(0, 2))
-  val data = Fill(4, count)
-
-  val (s_idle :: s_wreq :: s_wresp :: s_rreq :: s_rresp ::
-       s_finished :: Nil) = Enum(Bits(), 6)
-  val state = Reg(init = s_idle)
-
-  when (state === s_idle && io.start) { state := s_wreq }
-  when (state === s_wreq && io.mem.acquire.ready) { state := s_wresp }
-  when (state === s_wresp && io.mem.grant.valid) {
-    count := count + UInt(1)
-    when (count === UInt(nChecks - 1)) {
-      state := s_rreq
-    } .otherwise {
-      state := s_wreq
-    }
-  }
-
-  when (state === s_rreq && io.mem.acquire.ready) { state := s_rresp }
-  when (state === s_rresp && io.mem.grant.valid) {
-    count := count + UInt(1)
-    when (count === UInt(nChecks - 1)) {
-      state := s_finished
-    } .otherwise {
-      state := s_rreq
-    }
-  }
-
-  val blockOffsetBits = p(CacheBlockOffsetBits)
-  val byteAddrBits = log2Up(p(TLKey(p(TLId))).writeMaskBits)
-
-  io.mem.acquire.valid := (state === s_wreq) || (state === s_rreq)
-  io.mem.acquire.bits := Mux(state === s_wreq,
-    Put(
-      client_xact_id = UInt(0),
-      addr_block = addr >> UInt(blockOffsetBits),
-      addr_beat = addr(blockOffsetBits - 1, byteAddrBits),
-      data = Mux(count(0), data << UInt(32), data),
-      wmask = Some(FillInterleaved(4, UIntToOH(count(0))))),
-    Get(
-      client_xact_id = UInt(0),
-      addr_block = addr >> UInt(blockOffsetBits),
-      addr_beat = addr(blockOffsetBits - 1, byteAddrBits),
-      addr_byte = addr(byteAddrBits - 1, 0),
-      operand_size = MT_W,
-      alloc = Bool(false)))
-  io.mem.grant.ready := (state === s_wresp) || (state === s_rresp)
-
-  assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
-    Mux(count(0),
-      io.mem.grant.bits.data(63, 32) === data,
-      io.mem.grant.bits.data(31, 0) === data),
-    "Test Driver got incorrect data")
-
-  io.finished := (state === s_finished)
-}
-
-class SmiConverterTest(implicit p: Parameters) extends UnitTest {
-  val outermostParams = p.alterPartial({ case TLId => "Outermost" })
-
-  val smimem = Module(new SmiMem(32, 64))
-  val conv = Module(new SmiIOTileLinkIOConverter(32, 6)(outermostParams))
-  val driver = Module(new SmiConverterTestDriver()(outermostParams))
-
-  conv.io.tl <> driver.io.mem
-  smimem.io <> conv.io.smi
-  driver.io.start := io.start
-  io.finished := driver.io.finished
-}
-
-
diff --git a/groundtest/src/main/scala/unittests/TileLink.scala b/groundtest/src/main/scala/unittests/TileLink.scala
new file mode 100644
index 00000000..21b0584e
--- /dev/null
+++ b/groundtest/src/main/scala/unittests/TileLink.scala
@@ -0,0 +1,74 @@
+package groundtest.unittests
+
+
+import Chisel._
+import junctions._
+import uncore.devices._
+import uncore.tilelink._
+import uncore.converters._
+import groundtest.common._
+import cde.Parameters
+
+class SmiConverterTest(implicit val p: Parameters) extends UnitTest
+    with HasTileLinkParameters {
+  val outermostParams = p.alterPartial({ case TLId => "Outermost" })
+
+  val smiWidth = 32
+  val smiDepth = 64
+  val tlDepth = (smiWidth * smiDepth) / tlDataBits
+
+  val smimem = Module(new SmiMem(smiWidth, smiDepth))
+  val conv = Module(new SmiIOTileLinkIOConverter(
+    smiWidth, log2Up(smiDepth))(outermostParams))
+  val driver = Module(new DriverSet(
+    (driverParams: Parameters) => {
+      implicit val p = driverParams
+      Seq(
+        Module(new PutSweepDriver(tlDepth)),
+        Module(new PutMaskDriver(smiWidth / 8)),
+        Module(new PutBlockSweepDriver(tlDepth / tlDataBeats)))
+    })(outermostParams))
+
+  conv.io.tl <> driver.io.mem
+  smimem.io <> conv.io.smi
+  driver.io.start := io.start
+  io.finished := driver.io.finished
+}
+
+class ROMSlaveTest(implicit p: Parameters) extends UnitTest {
+  implicit val testName = "ROMSlaveTest"
+  val romdata = Seq(
+    BigInt("01234567deadbeef", 16),
+    BigInt("ab32fee8d00dfeed", 16))
+  val rombytes = romdata.map(_.toByteArray.reverse).flatten
+  val rom = Module(new ROMSlave(rombytes))
+  val driver = Module(new DriverSet(
+    (driverParams: Parameters) => {
+      implicit val p = driverParams
+      Seq(
+        Module(new GetMultiWidthDriver),
+        Module(new GetSweepDriver(romdata)),
+        Module(new GetBlockSweepDriver(romdata)))
+    }))
+  rom.io <> driver.io.mem
+  driver.io.start := io.start
+  io.finished := driver.io.finished
+}
+
+class TileLinkRAMTest(implicit val p: Parameters)
+    extends UnitTest with HasTileLinkParameters {
+
+  val depth = 2 * tlDataBeats
+  val ram = Module(new TileLinkTestRAM(depth))
+  val driver = Module(new DriverSet(
+    (driverParams: Parameters) => {
+      implicit val p = driverParams
+      Seq(
+        Module(new PutSweepDriver(depth)),
+        Module(new PutMaskDriver),
+        Module(new PutBlockSweepDriver(depth / tlDataBeats)))
+    }))
+  ram.io <> driver.io.mem
+  driver.io.start := io.start
+  io.finished := driver.io.finished
+}