diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala
index e33f4865..73fd4f61 100644
--- a/rocket/src/main/scala/dcache.scala
+++ b/rocket/src/main/scala/dcache.scala
@@ -45,6 +45,11 @@ class ioDCacheDM extends Bundle() {
   val mem = new ioDcache().flip();
 }
 
+class ioDCacheHella extends Bundle() {
+  val cpu = new ioDmem();
+  val mem = new ioDcache().flip();
+}
+
 class rocketDCacheStoreGen extends Component {
   val io = new Bundle {
     val req_type      = Bits(3, INPUT);
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 70d5fade..9d16d98e 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -541,7 +541,7 @@ class AMOALU extends Component {
 }
 
 class HellaCache(lines: Int) extends Component {
-  val io = new ioDCacheDM();
+  val io = new ioDCacheHella();
   
   val addrbits = PADDR_BITS;
   val indexbits = log2up(lines);
@@ -602,6 +602,22 @@ class HellaCache(lines: Int) extends Component {
     }
   }
 
+  // refill counter
+  val rr_count = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
+  val rr_count_next = rr_count + UFix(1)
+  when (io.mem.resp_val) { rr_count <== rr_count_next }
+
+  val misaligned =
+    (((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && (r_cpu_req_idx(0) != Bits(0))) ||
+    (((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0))) ||
+    ((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0)));
+    
+  io.cpu.xcpt_ma_ld := r_cpu_req_val_ && r_req_read && misaligned
+  io.cpu.xcpt_ma_st := r_cpu_req_val_ && r_req_write && misaligned
+
+}
+
+class HellaCacheDM(lines: Int) extends HellaCache(lines) {
   // tags
   val meta = new MetaDataArray(lines)
   val meta_arb = (new Arbiter(3)) { new MetaArrayReq() }
@@ -632,11 +648,6 @@ class HellaCache(lines: Int) extends Component {
   val tag_miss = r_cpu_req_val && !tag_match
   val dirty = meta.io.resp.valid && meta.io.resp.dirty
 
-  // refill counter
-  val rr_count = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
-  val rr_count_next = rr_count + UFix(1)
-  when (io.mem.resp_val) { rr_count <== rr_count_next }
-
   // refill response
   val block_during_refill = !io.mem.resp_val && (rr_count != UFix(0))
   data_arb.io.in(0).valid := io.mem.resp_val || block_during_refill
@@ -791,14 +802,6 @@ class HellaCache(lines: Int) extends Component {
   io.cpu.resp_data := loadgen.io.dout
   io.cpu.resp_data_subword := loadgen.io.r_dout_subword
                       
-  val misaligned =
-    (((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && (r_cpu_req_idx(0) != Bits(0))) ||
-    (((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0))) ||
-    ((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0)));
-    
-  io.cpu.xcpt_ma_ld := r_cpu_req_val_ && r_req_read && misaligned
-  io.cpu.xcpt_ma_st := r_cpu_req_val_ && r_req_write && misaligned
-
   wb.io.mem_req.ready := io.mem.req_rdy
   io.mem.req_val   := wb.io.mem_req.valid
   io.mem.req_rw    := wb.io.mem_req.bits.rw
diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala
index d84d333e..be9bb311 100644
--- a/rocket/src/main/scala/top.scala
+++ b/rocket/src/main/scala/top.scala
@@ -17,7 +17,7 @@ class Top() extends Component {
   val cpu       = new rocketProc();
   val icache    = new rocketICacheDM(128); // # 64 byte cache lines
   val icache_pf = new rocketIPrefetcher();
-  val dcache    = new HellaCache(128);
+  val dcache    = new HellaCacheDM(128);
   val arbiter   = new rocketMemArbiter();
 
   arbiter.io.mem    ^^ io.mem; 
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index ac182310..1cbc7674 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -2,8 +2,14 @@ package Top
 {
 
 import Chisel._
-import Node._;
-import scala.math._;
+import Node._
+import scala.math._
+
+object foldR
+{
+  def apply[T <: Bits](x: Seq[T], f: (T, T) => T): T =
+    if (x.length == 1) x(0) else f(x(0), foldR(x.slice(1, x.length), f))
+}
 
 object log2up
 {