riscv/rocket-chip
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Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2

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Conflicts:
	chisel
	riscv-hwacha
	riscv-rocket
	uncore
This commit is contained in:
Henry Cook 2013-08-15 16:39:30 -07:00
commit 6b20556661
4 changed files with 4 additions and 4 deletions
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2
chisel

@ -1 +1 @@
Subproject commit 58cb89a8831312a6a875372f9142fb444a593589 Subproject commit 8eb2d8a20d97722f4b5f40ab74eb19c8585d690f

2
riscv-rocket

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Subproject commit 744846b72e7af011aca74fa5ded131552152af62 Subproject commit 4461c5f4ed3e3f8192c7497e2431ccf1a7ff12cb

2
src/main/scala/RocketChip.scala
View File

@ -14,7 +14,7 @@ object DummyTopLevelConstants {
val HTIF_WIDTH = 16 val HTIF_WIDTH = 16
val ENABLE_SHARING = true val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true val ENABLE_CLEAN_EXCLUSIVE = true
val HAS_VEC = true val HAS_VEC = false
val HAS_FPU = true val HAS_FPU = true
val NL2_REL_XACTS = 1 val NL2_REL_XACTS = 1
val NL2_ACQ_XACTS = 8 val NL2_ACQ_XACTS = 8

2
uncore

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Subproject commit 113ba96c49b7cff56ab93e55768838d59f8491d3 Subproject commit 4a8bb15978e2563aabbe41ec8797c5abbdaaf216