diff --git a/chisel b/chisel
index 58cb89a8..8eb2d8a2 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit 58cb89a8831312a6a875372f9142fb444a593589
+Subproject commit 8eb2d8a20d97722f4b5f40ab74eb19c8585d690f
diff --git a/riscv-rocket b/riscv-rocket
index 744846b7..4461c5f4 160000
--- a/riscv-rocket
+++ b/riscv-rocket
@@ -1 +1 @@
-Subproject commit 744846b72e7af011aca74fa5ded131552152af62
+Subproject commit 4461c5f4ed3e3f8192c7497e2431ccf1a7ff12cb
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 5ba1b8b2..5c13e6a4 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -14,7 +14,7 @@ object DummyTopLevelConstants {
   val HTIF_WIDTH = 16
   val ENABLE_SHARING = true
   val ENABLE_CLEAN_EXCLUSIVE = true
-  val HAS_VEC = true
+  val HAS_VEC = false
   val HAS_FPU = true
   val NL2_REL_XACTS = 1
   val NL2_ACQ_XACTS = 8
diff --git a/uncore b/uncore
index 113ba96c..4a8bb159 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 113ba96c49b7cff56ab93e55768838d59f8491d3
+Subproject commit 4a8bb15978e2563aabbe41ec8797c5abbdaaf216