cache/tlb bugfixes, increased memory size to 256meg
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@ -182,7 +182,7 @@ object Constants
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// physical memory size (# 8K pages)
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// physical memory size (# 8K pages)
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// if you change this value, make sure to also change MEMORY_SIZE variable in memif.h
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// if you change this value, make sure to also change MEMORY_SIZE variable in memif.h
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val MEMSIZE_PAGES = 8192; // 64 megs
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val MEMSIZE_PAGES = 0x8000; // 256 megs
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val MEMSIZE_BYTES = MEMSIZE_PAGES*8192;
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val MEMSIZE_BYTES = MEMSIZE_PAGES*8192;
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val HAVE_FPU = Bool(false);
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val HAVE_FPU = Bool(false);
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@ -422,8 +422,8 @@ class rocketCtrl extends Component
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// replay mem stage PC on a DTLB miss
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// replay mem stage PC on a DTLB miss
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val replay_mem = io.dtlb_miss;
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val replay_mem = io.dtlb_miss;
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val kill_ex = replay_ex || replay_mem;
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val kill_mem = mem_exception || replay_mem;
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val kill_mem = mem_exception || replay_mem;
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val kill_ex = replay_ex || kill_mem;
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io.dpath.sel_pc :=
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io.dpath.sel_pc :=
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Mux(replay_mem, PC_MEM, // dtlb miss
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Mux(replay_mem, PC_MEM, // dtlb miss
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@ -352,8 +352,8 @@ class rocketDCacheDM(lines: Int) extends Component {
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r_cpu_resp_val;
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r_cpu_resp_val;
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val misaligned =
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val misaligned =
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((r_cpu_req_type === MT_H) && r_cpu_req_idx(0).toBool) ||
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(((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && r_cpu_req_idx(0).toBool) ||
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((r_cpu_req_type === MT_W) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
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(((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
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((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0,3)));
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((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0,3)));
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io.cpu.xcpt_ma_ld := r_cpu_req_val && r_req_load && misaligned;
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io.cpu.xcpt_ma_ld := r_cpu_req_val && r_req_load && misaligned;
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@ -177,7 +177,7 @@ class rocketITLB(entries: Int) extends Component
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((status_s && !sx_array(tag_hit_addr).toBool) ||
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((status_s && !sx_array(tag_hit_addr).toBool) ||
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(status_u && !ux_array(tag_hit_addr).toBool));
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(status_u && !ux_array(tag_hit_addr).toBool));
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io.cpu.exception := access_fault || outofrange;
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io.cpu.exception := access_fault; //|| outofrange;
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io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && (!r_cpu_req_val || tag_hit), Bool(true));
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io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && (!r_cpu_req_val || tag_hit), Bool(true));
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io.cpu.resp_miss := tlb_miss || (state != s_ready);
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io.cpu.resp_miss := tlb_miss || (state != s_ready);
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io.cpu.resp_ppn := Mux(status_vm, tag_ram(tag_hit_addr), r_cpu_req_vpn(PPN_BITS-1,0)).toUFix;
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io.cpu.resp_ppn := Mux(status_vm, tag_ram(tag_hit_addr), r_cpu_req_vpn(PPN_BITS-1,0)).toUFix;
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