diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index 612a7ec0..96a73e9f 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -182,7 +182,7 @@ object Constants
   
   // physical memory size (# 8K pages)
   // if you change this value, make sure to also change MEMORY_SIZE variable in memif.h
-  val MEMSIZE_PAGES = 8192; // 64 megs
+  val MEMSIZE_PAGES = 0x8000; // 256 megs
   val MEMSIZE_BYTES = MEMSIZE_PAGES*8192;
   
   val HAVE_FPU = Bool(false);
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 4e8be7df..2277ad4a 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -422,8 +422,8 @@ class rocketCtrl extends Component
   
   // replay mem stage PC on a DTLB miss
   val replay_mem = io.dtlb_miss;
-  val kill_ex    = replay_ex || replay_mem;
   val kill_mem   = mem_exception || replay_mem;
+  val kill_ex    = replay_ex || kill_mem;
 
   io.dpath.sel_pc :=
     Mux(replay_mem,                   PC_MEM,  // dtlb miss
diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala
index fe2962d3..863c0855 100644
--- a/rocket/src/main/scala/dcache.scala
+++ b/rocket/src/main/scala/dcache.scala
@@ -352,8 +352,8 @@ class rocketDCacheDM(lines: Int) extends Component {
                       r_cpu_resp_val;
                       
   val misaligned =
-    ((r_cpu_req_type === MT_H) && r_cpu_req_idx(0).toBool) ||
-    ((r_cpu_req_type === MT_W) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
+    (((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && r_cpu_req_idx(0).toBool) ||
+    (((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
     ((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0,3)));
     
   io.cpu.xcpt_ma_ld := r_cpu_req_val && r_req_load && misaligned;
diff --git a/rocket/src/main/scala/itlb.scala b/rocket/src/main/scala/itlb.scala
index 0df38144..b6e82faf 100644
--- a/rocket/src/main/scala/itlb.scala
+++ b/rocket/src/main/scala/itlb.scala
@@ -177,7 +177,7 @@ class rocketITLB(entries: Int) extends Component
     ((status_s && !sx_array(tag_hit_addr).toBool) ||
      (status_u && !ux_array(tag_hit_addr).toBool));
 
-  io.cpu.exception := access_fault || outofrange;
+  io.cpu.exception := access_fault; //|| outofrange;
   io.cpu.req_rdy   := Mux(status_vm, (state === s_ready) && (!r_cpu_req_val || tag_hit), Bool(true));
   io.cpu.resp_miss := tlb_miss || (state != s_ready);
   io.cpu.resp_ppn := Mux(status_vm, tag_ram(tag_hit_addr), r_cpu_req_vpn(PPN_BITS-1,0)).toUFix;