riscv/rocket-chip
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cache/tlb bugfixes, increased memory size to 256meg

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Rimas Avizienis
2011-11-13 13:06:35 -08:00
parent 29d44b8bc5
commit 67c7e7e28f
4 changed files with 5 additions and 5 deletions
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4
rocket/src/main/scala/dcache.scala
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@ -352,8 +352,8 @@ class rocketDCacheDM(lines: Int) extends Component {
r_cpu_resp_val;
val misaligned =
((r_cpu_req_type === MT_H) && r_cpu_req_idx(0).toBool) ||
((r_cpu_req_type === MT_W) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
(((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && r_cpu_req_idx(0).toBool) ||
(((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0,3)));
io.cpu.xcpt_ma_ld := r_cpu_req_val && r_req_load && misaligned;