riscv/rocket-chip
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cache/tlb bugfixes, increased memory size to 256meg

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This commit is contained in:
Rimas Avizienis
2011-11-13 13:06:35 -08:00
parent 29d44b8bc5
commit 67c7e7e28f
4 changed files with 5 additions and 5 deletions
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2
rocket/src/main/scala/ctrl.scala
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@ -422,8 +422,8 @@ class rocketCtrl extends Component
// replay mem stage PC on a DTLB miss
val replay_mem = io.dtlb_miss;
val kill_ex = replay_ex || replay_mem;
val kill_mem = mem_exception || replay_mem;
val kill_ex = replay_ex || kill_mem;
io.dpath.sel_pc :=
Mux(replay_mem, PC_MEM, // dtlb miss