riscv/rocket-chip
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cleanup before adding dtlb

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This commit is contained in:
Rimas Avizienis 2011-11-09 23:27:29 -08:00
parent 9aca403aa8
commit 6664af3bc0
3 changed files with 13 additions and 18 deletions
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1
rocket/src/main/scala/consts.scala
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@ -162,6 +162,7 @@ object Constants
val ASID_BITS = 7;
val PERM_BITS = 6;
val DTLB_ENTRIES = 8;
val ITLB_ENTRIES = 8;
val HAVE_FPU = Bool(false);

17
rocket/src/main/scala/cpu.scala
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@ -45,6 +45,7 @@ class rocketProc extends Component
val ctrl = new rocketCtrl();
val dpath = new rocketDpath();
val dtlb = new rocketDTLB(ITLB_ENTRIES);
val itlb = new rocketITLB(ITLB_ENTRIES);
val ptw = new rocketPTW();
val arb = new rocketDmemArbiter();
@ -60,38 +61,38 @@ class rocketProc extends Component
dpath.io.host ^^ io.host;
dpath.io.debug ^^ io.debug;
// FIXME: make this less verbose
// connect ITLB to I$, ctrl, dpath
itlb.io.cpu.invalidate := Bool(false);
itlb.io.cpu.status := dpath.io.ctrl.status;
itlb.io.cpu.req_val := ctrl.io.imem.req_val;
ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
itlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
// itlb.io.cpu.req_vpn := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
itlb.io.cpu.req_addr := dpath.io.imem.req_addr;
io.imem.req_val := itlb.io.cpu.resp_val;
io.imem.req_addr := itlb.io.cpu.resp_addr;
ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
ctrl.io.imem.resp_val := io.imem.resp_val;
ctrl.io.itlb_xcpt := itlb.io.cpu.exception;
// connect page table walker to TLBs, page table base register (from PCR)
// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
ptw.io.itlb <> itlb.io.ptw;
ptw.io.ptbr := dpath.io.ptbr;
arb.io.ptw <> ptw.io.dmem;
arb.io.mem ^^ io.dmem
// FIXME: make this less verbose
// connect arbiter to ctrl+dpath
arb.io.cpu.req_val := ctrl.io.dmem.req_val;
arb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
arb.io.cpu.req_type := ctrl.io.dmem.req_type;
arb.io.cpu.req_addr := dpath.io.dmem.req_addr;
arb.io.cpu.req_data := dpath.io.dmem.req_data;
arb.io.cpu.req_tag := dpath.io.dmem.req_tag;
ctrl.io.dmem.req_rdy := arb.io.cpu.req_rdy;
ctrl.io.dmem.resp_miss := arb.io.cpu.resp_miss;
ctrl.io.dmem.resp_val := arb.io.cpu.resp_val;
dpath.io.dmem.resp_val := arb.io.cpu.resp_val;
dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
dpath.io.dmem.resp_data := arb.io.cpu.resp_data;

11
rocket/src/main/scala/dpath.scala
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@ -17,7 +17,6 @@ class ioDpathAll extends Bundle()
val ctrl = new ioCtrlDpath().flip();
val debug = new ioDebug();
val dmem = new ioDmem(List("req_addr", "req_data", "req_tag", "resp_val", "resp_tag", "resp_data")).flip();
// val imem = new ioImem(List("req_addr", "resp_data")).flip();
val imem = new ioDpathImem();
val ptbr = UFix(PADDR_BITS, 'output);
}
@ -127,6 +126,7 @@ class rocketDpath extends Component
val ex_sign_extend_split =
Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));
// FIXME: which bits to extract should be calculated based on VADDR_BITS
val branch_adder_rhs =
Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(41,0), UFix(0, 1)),
Cat(Fill(17, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0, 1)));
@ -154,7 +154,6 @@ class rocketDpath extends Component
if_reg_pc <== if_next_pc;
}
io.imem.req_addr :=
Mux(io.ctrl.stallf, if_reg_pc,
if_next_pc);
@ -199,8 +198,7 @@ class rocketDpath extends Component
UFix(0, 5)))));
// moved this here to avoid having to do forward declaration
// TODO: cleanup
// FIXME: cleanup
// 64/32 bit load handling (in mem stage)
val dmem_resp_pos = io.dmem.resp_tag(7,5).toUFix;
val dmem_resp_type = io.dmem.resp_tag(10,8);
@ -359,11 +357,6 @@ class rocketDpath extends Component
pcr.io.host.from ^^ io.host.from;
pcr.io.host.to ^^ io.host.to;
// pcr.io.eret := ex_reg_ctrl_eret;
// pcr.io.exception := ex_reg_ctrl_exception;
// pcr.io.cause := ex_reg_ctrl_cause;
// pcr.io.pc := ex_reg_pc;
io.ctrl.status := pcr.io.status;
io.ptbr := pcr.io.ptbr;
io.debug.error_mode := pcr.io.debug.error_mode;