diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index 344eace5..794e54d2 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -162,6 +162,7 @@ object Constants
   val ASID_BITS = 7;
   val PERM_BITS = 6;
   
+  val DTLB_ENTRIES = 8;
   val ITLB_ENTRIES = 8;
   
   val HAVE_FPU = Bool(false);
diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala
index 3b09b0f1..b68a9316 100644
--- a/rocket/src/main/scala/cpu.scala
+++ b/rocket/src/main/scala/cpu.scala
@@ -45,6 +45,7 @@ class rocketProc extends Component
   val ctrl  = new rocketCtrl();      
   val dpath = new rocketDpath();
 
+  val dtlb  = new rocketDTLB(ITLB_ENTRIES);
   val itlb  = new rocketITLB(ITLB_ENTRIES);
   val ptw   = new rocketPTW();
   val arb   = new rocketDmemArbiter();
@@ -60,38 +61,38 @@ class rocketProc extends Component
   dpath.io.host             ^^ io.host;
   dpath.io.debug            ^^ io.debug;
 
+  // FIXME: make this less verbose
+  // connect ITLB to I$, ctrl, dpath
   itlb.io.cpu.invalidate  := Bool(false);
   itlb.io.cpu.status      := dpath.io.ctrl.status;
-  itlb.io.cpu.req_val     := ctrl.io.imem.req_val;
-  ctrl.io.imem.req_rdy    := itlb.io.cpu.req_rdy && io.imem.req_rdy;
-  
+  itlb.io.cpu.req_val     := ctrl.io.imem.req_val;  
   itlb.io.cpu.req_asid    := Bits(0,ASID_BITS); // FIXME: connect to PCR
-//  itlb.io.cpu.req_vpn     := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
   itlb.io.cpu.req_addr    := dpath.io.imem.req_addr;
-  
   io.imem.req_val         := itlb.io.cpu.resp_val;
   io.imem.req_addr        := itlb.io.cpu.resp_addr;
-  
+  ctrl.io.imem.req_rdy    := itlb.io.cpu.req_rdy && io.imem.req_rdy;  
   ctrl.io.imem.resp_val   := io.imem.resp_val;
   ctrl.io.itlb_xcpt       := itlb.io.cpu.exception;
   
+  // connect page table walker to TLBs, page table base register (from PCR)
+  // and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
+  
   ptw.io.itlb             <> itlb.io.ptw;
   ptw.io.ptbr             := dpath.io.ptbr;
-  
   arb.io.ptw              <> ptw.io.dmem;
   arb.io.mem              ^^ io.dmem
   
+  // FIXME: make this less verbose
+  // connect arbiter to ctrl+dpath
   arb.io.cpu.req_val      := ctrl.io.dmem.req_val;
   arb.io.cpu.req_cmd      := ctrl.io.dmem.req_cmd;
   arb.io.cpu.req_type     := ctrl.io.dmem.req_type;
   arb.io.cpu.req_addr     := dpath.io.dmem.req_addr;
   arb.io.cpu.req_data     := dpath.io.dmem.req_data;
   arb.io.cpu.req_tag      := dpath.io.dmem.req_tag;
-  
   ctrl.io.dmem.req_rdy    := arb.io.cpu.req_rdy;
   ctrl.io.dmem.resp_miss  := arb.io.cpu.resp_miss;
   ctrl.io.dmem.resp_val   := arb.io.cpu.resp_val;
-  
   dpath.io.dmem.resp_val  := arb.io.cpu.resp_val;
   dpath.io.dmem.resp_tag  := arb.io.cpu.resp_tag;
   dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index a759b8ea..e9218261 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -17,7 +17,6 @@ class ioDpathAll extends Bundle()
   val ctrl  = new ioCtrlDpath().flip();
   val debug = new ioDebug();
   val dmem  = new ioDmem(List("req_addr", "req_data", "req_tag", "resp_val", "resp_tag", "resp_data")).flip();
-//   val imem  = new ioImem(List("req_addr", "resp_data")).flip();
   val imem  = new ioDpathImem();
   val ptbr = UFix(PADDR_BITS, 'output);
 }
@@ -127,6 +126,7 @@ class rocketDpath extends Component
   val ex_sign_extend_split = 
     Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));
 
+  // FIXME: which bits to extract should be calculated based on VADDR_BITS
   val branch_adder_rhs =
     Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(41,0), UFix(0, 1)),
         Cat(Fill(17, ex_reg_inst(31)), ex_reg_inst(31,7),          UFix(0, 1)));
@@ -153,7 +153,6 @@ class rocketDpath extends Component
   when (!io.ctrl.stallf) {
     if_reg_pc <== if_next_pc;
   }
- 
 
   io.imem.req_addr :=
     Mux(io.ctrl.stallf, if_reg_pc,
@@ -199,8 +198,7 @@ class rocketDpath extends Component
         UFix(0, 5)))));
 
   // moved this here to avoid having to do forward declaration
-  // TODO: cleanup
-  
+  // FIXME: cleanup
   // 64/32 bit load handling (in mem stage)
   val dmem_resp_pos   = io.dmem.resp_tag(7,5).toUFix;
   val dmem_resp_type  = io.dmem.resp_tag(10,8);
@@ -358,11 +356,6 @@ class rocketDpath extends Component
   pcr.io.host.from_wen ^^ io.host.from_wen;
   pcr.io.host.from     ^^ io.host.from;
   pcr.io.host.to       ^^ io.host.to;
-
-//   pcr.io.eret      	:= ex_reg_ctrl_eret;
-//   pcr.io.exception 	:= ex_reg_ctrl_exception;
-//   pcr.io.cause 			:= ex_reg_ctrl_cause;
-//   pcr.io.pc					:= ex_reg_pc;
   
   io.ctrl.status       := pcr.io.status;
   io.ptbr              := pcr.io.ptbr;