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Merge remote-tracking branch 'origin/master' into rocc-fpu-port

This commit is contained in:
Colin Schmidt 2015-10-22 16:38:28 -07:00
commit 652fb393a3
15 changed files with 15 additions and 1 deletions

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@ -6,5 +6,5 @@ name := "rocket"
scalaVersion := "2.11.6" scalaVersion := "2.11.6"
libraryDependencies ++= (Seq("chisel", "hardfloat", "uncore", "junctions").map { libraryDependencies ++= (Seq("chisel", "hardfloat", "uncore", "junctions", "cde").map {
dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten

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@ -4,6 +4,7 @@ package rocket
import Chisel._ import Chisel._
import uncore._ import uncore._
import cde.{Parameters, Field}
class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
{ {

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@ -4,6 +4,7 @@ package rocket
import Chisel._ import Chisel._
import junctions._ import junctions._
import cde.{Parameters, Field}
import Util._ import Util._
case object BtbKey extends Field[BtbParameters] case object BtbKey extends Field[BtbParameters]

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@ -5,6 +5,7 @@ package rocket
import Chisel._ import Chisel._
import Util._ import Util._
import Instructions._ import Instructions._
import cde.{Parameters, Field}
import uncore._ import uncore._
import scala.math._ import scala.math._

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@ -3,6 +3,7 @@
package rocket package rocket
import Chisel._ import Chisel._
import cde.{Parameters, Field}
import Instructions._ import Instructions._
object ALU object ALU

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@ -7,6 +7,7 @@ import Instructions._
import Util._ import Util._
import FPConstants._ import FPConstants._
import uncore.constants.MemoryOpConstants._ import uncore.constants.MemoryOpConstants._
import cde.{Parameters, Field}
case object SFMALatency case object SFMALatency
case object DFMALatency case object DFMALatency

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@ -3,6 +3,7 @@ package rocket
import Chisel._ import Chisel._
import uncore._ import uncore._
import Util._ import Util._
import cde.{Parameters, Field}
class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) { class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
val pc = UInt(width = vaddrBitsExtended) val pc = UInt(width = vaddrBitsExtended)

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@ -3,6 +3,7 @@ package rocket
import Chisel._ import Chisel._
import uncore._ import uncore._
import Util._ import Util._
import cde.{Parameters, Field}
trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters { trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
val outerDataBeats = p(TLKey(p(TLId))).dataBeats val outerDataBeats = p(TLKey(p(TLId))).dataBeats

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@ -5,6 +5,7 @@ package rocket
import Chisel._ import Chisel._
import uncore._ import uncore._
import junctions._ import junctions._
import cde.{Parameters, Field}
import Util._ import Util._
case object WordBits extends Field[Int] case object WordBits extends Field[Int]

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@ -5,6 +5,7 @@ package rocket
import Chisel._ import Chisel._
import uncore._ import uncore._
import Util._ import Util._
import cde.{Parameters, Field}
class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
val addr = UInt(width = vpnBits) val addr = UInt(width = vpnBits)

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@ -5,6 +5,7 @@ package rocket
import Chisel._ import Chisel._
import uncore._ import uncore._
import Util._ import Util._
import cde.{Parameters, Field}
case object RoccMaxTaggedMemXacts extends Field[Int] case object RoccMaxTaggedMemXacts extends Field[Int]
case object RoccNMemChannels extends Field[Int] case object RoccNMemChannels extends Field[Int]

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@ -6,6 +6,7 @@ import Chisel._
import junctions._ import junctions._
import uncore._ import uncore._
import Util._ import Util._
import cde.{Parameters, Field}
case object UseFPU extends Field[Boolean] case object UseFPU extends Field[Boolean]
case object FDivSqrt extends Field[Boolean] case object FDivSqrt extends Field[Boolean]

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@ -5,6 +5,7 @@ package rocket
import Chisel._ import Chisel._
import uncore._ import uncore._
import Util._ import Util._
import cde.{Parameters, Field}
case object CoreName extends Field[String] case object CoreName extends Field[String]
case object BuildRoCC extends Field[Option[Parameters => RoCC]] case object BuildRoCC extends Field[Option[Parameters => RoCC]]

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@ -6,6 +6,7 @@ import Chisel._
import Util._ import Util._
import junctions._ import junctions._
import scala.math._ import scala.math._
import cde.{Parameters, Field}
case object NTLBEntries extends Field[Int] case object NTLBEntries extends Field[Int]

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@ -5,6 +5,7 @@ package rocket
import Chisel._ import Chisel._
import uncore._ import uncore._
import scala.math._ import scala.math._
import cde.{Parameters, Field}
object Util { object Util {
implicit def intToUInt(x: Int): UInt = UInt(x) implicit def intToUInt(x: Int): UInt = UInt(x)