diff --git a/rocket/build.sbt b/rocket/build.sbt
index bfc36cc5..97c51700 100644
--- a/rocket/build.sbt
+++ b/rocket/build.sbt
@@ -6,5 +6,5 @@ name := "rocket"
 
 scalaVersion := "2.11.6"
 
-libraryDependencies ++= (Seq("chisel", "hardfloat", "uncore", "junctions").map {
+libraryDependencies ++= (Seq("chisel", "hardfloat", "uncore", "junctions", "cde").map {
   dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten
diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index 14f20735..27bfcc86 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -4,6 +4,7 @@ package rocket
 
 import Chisel._
 import uncore._
+import cde.{Parameters, Field}
 
 class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
 {
diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index 84295f27..3aa1b6a6 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -4,6 +4,7 @@ package rocket
 
 import Chisel._
 import junctions._
+import cde.{Parameters, Field}
 import Util._
 
 case object BtbKey extends Field[BtbParameters]
diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index a6862b45..5898941c 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import Util._
 import Instructions._
+import cde.{Parameters, Field}
 import uncore._
 import scala.math._
 
diff --git a/rocket/src/main/scala/dpath_alu.scala b/rocket/src/main/scala/dpath_alu.scala
index 5142c611..58942266 100644
--- a/rocket/src/main/scala/dpath_alu.scala
+++ b/rocket/src/main/scala/dpath_alu.scala
@@ -3,6 +3,7 @@
 package rocket
 
 import Chisel._
+import cde.{Parameters, Field}
 import Instructions._
 
 object ALU
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 8e2d8f9e..5b4cf1ee 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -7,6 +7,7 @@ import Instructions._
 import Util._
 import FPConstants._
 import uncore.constants.MemoryOpConstants._
+import cde.{Parameters, Field}
 
 case object SFMALatency
 case object DFMALatency
diff --git a/rocket/src/main/scala/frontend.scala b/rocket/src/main/scala/frontend.scala
index 2dce522b..36a5a2d0 100644
--- a/rocket/src/main/scala/frontend.scala
+++ b/rocket/src/main/scala/frontend.scala
@@ -3,6 +3,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
   val pc = UInt(width = vaddrBitsExtended)
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 76691620..1b3cf067 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -3,6 +3,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
   val outerDataBeats = p(TLKey(p(TLId))).dataBeats
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 7b6d4a11..2223ade0 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import junctions._
+import cde.{Parameters, Field}
 import Util._
 
 case object WordBits extends Field[Int]
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 6f1d8534..1a551bda 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
   val addr = UInt(width = vpnBits)
diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index e1612361..10f5e248 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 case object RoccMaxTaggedMemXacts extends Field[Int]
 case object RoccNMemChannels extends Field[Int]
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index c62470e5..21f59306 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -6,6 +6,7 @@ import Chisel._
 import junctions._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 case object UseFPU extends Field[Boolean]
 case object FDivSqrt extends Field[Boolean]
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index ce29b18e..c5e3e851 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}
 
 case object CoreName extends Field[String]
 case object BuildRoCC extends Field[Option[Parameters => RoCC]]
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index ee624896..8c6f9528 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -6,6 +6,7 @@ import Chisel._
 import Util._
 import junctions._
 import scala.math._
+import cde.{Parameters, Field}
 
 case object NTLBEntries extends Field[Int]
 
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index 2ac3a0b8..4050be5b 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore._
 import scala.math._
+import cde.{Parameters, Field}
 
 object Util {
   implicit def intToUInt(x: Int): UInt = UInt(x)