From 62765e96094bcc2adf2d126a0c80c5ba12a930f3 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Tue, 20 Oct 2015 18:56:22 -0700
Subject: [PATCH] L2 rowBits param bugfix

---
 src/main/scala/Configs.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 5044ca53..3216f849 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -193,7 +193,7 @@ class WithL2Cache extends ChiselConfig(
                           site(NBanksPerMemoryChannel)*site(NMemoryChannels)) /
                             site(NWays)
       case NWays => Knob("L2_WAYS")
-      case RowBits => site(TLKey(site(TLId))).dataBits
+      case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
     }: PartialFunction[Any,Any] 
     case NAcquireTransactors => 2
     case NSecondaryMisses => 4