added ld/st misaligned exceptions
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fbd44ea936
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5f4b15b809
@ -85,7 +85,8 @@ class rocketProc extends Component
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ctrl.io.xcpt_dtlb_st := dtlb.io.cpu.xcpt_st;
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ctrl.io.xcpt_dtlb_st := dtlb.io.cpu.xcpt_st;
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ctrl.io.dtlb_busy := dtlb.io.cpu.resp_busy;
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ctrl.io.dtlb_busy := dtlb.io.cpu.resp_busy;
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ctrl.io.dtlb_miss := dtlb.io.cpu.resp_miss;
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ctrl.io.dtlb_miss := dtlb.io.cpu.resp_miss;
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// io.dmem.dtlb_miss := dtlb.io.cpu.resp_miss;
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ctrl.io.xcpt_ma_ld := io.dmem.xcpt_ma_ld;
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ctrl.io.xcpt_ma_st := io.dmem.xcpt_ma_st;
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// connect page table walker to TLBs, page table base register (from PCR)
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// connect page table walker to TLBs, page table base register (from PCR)
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// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
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// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
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@ -73,6 +73,8 @@ class ioCtrlAll extends Bundle()
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val xcpt_dtlb_ld = Bool('input);
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val xcpt_dtlb_ld = Bool('input);
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val xcpt_dtlb_st = Bool('input);
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val xcpt_dtlb_st = Bool('input);
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val xcpt_itlb = Bool('input);
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val xcpt_itlb = Bool('input);
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val xcpt_ma_ld = Bool('input);
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val xcpt_ma_st = Bool('input);
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}
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}
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class rocketCtrl extends Component
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class rocketCtrl extends Component
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@ -381,6 +383,8 @@ class rocketCtrl extends Component
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// exception handling
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// exception handling
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val mem_exception =
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val mem_exception =
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io.xcpt_ma_ld ||
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io.xcpt_ma_st ||
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io.xcpt_dtlb_ld ||
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io.xcpt_dtlb_ld ||
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io.xcpt_dtlb_st ||
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io.xcpt_dtlb_st ||
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mem_reg_xcpt_illegal ||
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mem_reg_xcpt_illegal ||
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@ -398,11 +402,11 @@ class rocketCtrl extends Component
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// interrupt
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// interrupt
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Mux(mem_reg_xcpt_syscall, UFix(6,5), // system call
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Mux(mem_reg_xcpt_syscall, UFix(6,5), // system call
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// breakpoint
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// breakpoint
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// misaligned load
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Mux(io.xcpt_ma_ld, UFix(8,5), // misaligned load
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// misaligned store
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Mux(io.xcpt_ma_st, UFix(9,5), // misaligned store
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Mux(io.xcpt_dtlb_ld, UFix(8,5), // load fault
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Mux(io.xcpt_dtlb_ld, UFix(10,5), // load fault
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Mux(io.xcpt_dtlb_st, UFix(9,5), // store fault
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Mux(io.xcpt_dtlb_st, UFix(11,5), // store fault
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UFix(0,5)))))))); // instruction address misaligned
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UFix(0,5)))))))))); // instruction address misaligned
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// write cause to PCR on an exception
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// write cause to PCR on an exception
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io.dpath.exception := mem_exception;
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io.dpath.exception := mem_exception;
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@ -18,6 +18,8 @@ class ioDmem(view: List[String] = null) extends Bundle(view) {
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// val req_addr = UFix(PADDR_BITS, 'input);
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// val req_addr = UFix(PADDR_BITS, 'input);
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val req_data = Bits(64, 'input);
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val req_data = Bits(64, 'input);
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val req_tag = Bits(5, 'input);
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val req_tag = Bits(5, 'input);
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val xcpt_ma_ld = Bool('output); // misaligned load
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val xcpt_ma_st = Bool('output); // misaligned store
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val resp_miss = Bool('output);
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val resp_miss = Bool('output);
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val resp_val = Bool('output);
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val resp_val = Bool('output);
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val resp_data = Bits(64, 'output);
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val resp_data = Bits(64, 'output);
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@ -151,16 +153,14 @@ class rocketDCacheDM_flush(lines: Int) extends Component {
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dcache.io.cpu.req_cmd := Mux(flushing, M_FLA, io.cpu.req_cmd);
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dcache.io.cpu.req_cmd := Mux(flushing, M_FLA, io.cpu.req_cmd);
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dcache.io.cpu.req_idx := Mux(flushing, Cat(flush_count, Bits(0,offsetbits)), io.cpu.req_idx);
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dcache.io.cpu.req_idx := Mux(flushing, Cat(flush_count, Bits(0,offsetbits)), io.cpu.req_idx);
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dcache.io.cpu.req_ppn := Mux(flushing, UFix(0,PPN_BITS), io.cpu.req_ppn);
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dcache.io.cpu.req_ppn := Mux(flushing, UFix(0,PPN_BITS), io.cpu.req_ppn);
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// dcache.io.cpu.req_addr :=
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// Mux(flushing, Cat(Bits(0,tagmsb-taglsb+1), flush_count, Bits(0,offsetbits)).toUFix,
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// io.cpu.req_addr);
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dcache.io.cpu.req_tag := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag);
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dcache.io.cpu.req_tag := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag);
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dcache.io.cpu.req_type := io.cpu.req_type;
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dcache.io.cpu.req_type := io.cpu.req_type;
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dcache.io.cpu.req_data ^^ io.cpu.req_data;
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dcache.io.cpu.req_data ^^ io.cpu.req_data;
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// dcache.io.cpu.dtlb_busy := io.cpu.dtlb_busy;
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dcache.io.cpu.dtlb_miss := io.cpu.dtlb_miss;
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dcache.io.cpu.dtlb_miss := io.cpu.dtlb_miss;
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dcache.io.mem ^^ io.mem;
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dcache.io.mem ^^ io.mem;
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io.cpu.xcpt_ma_ld := dcache.io.cpu.xcpt_ma_ld;
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io.cpu.xcpt_ma_st := dcache.io.cpu.xcpt_ma_st;
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io.cpu.req_rdy := dcache.io.cpu.req_rdy && !flush_waiting;
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io.cpu.req_rdy := dcache.io.cpu.req_rdy && !flush_waiting;
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io.cpu.resp_miss := dcache.io.cpu.resp_miss;
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io.cpu.resp_miss := dcache.io.cpu.resp_miss;
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io.cpu.resp_data := dcache.io.cpu.resp_data;
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io.cpu.resp_data := dcache.io.cpu.resp_data;
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@ -351,6 +351,14 @@ class rocketDCacheDM(lines: Int) extends Component {
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((state === s_resolve_miss) && r_req_flush) ||
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((state === s_resolve_miss) && r_req_flush) ||
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r_cpu_resp_val;
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r_cpu_resp_val;
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val misaligned =
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((r_cpu_req_type === MT_H) && r_cpu_req_idx(0).toBool) ||
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((r_cpu_req_type === MT_W) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
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((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0,3)));
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io.cpu.xcpt_ma_ld := r_cpu_req_val && r_req_load && misaligned;
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io.cpu.xcpt_ma_st := r_cpu_req_val && r_req_store && misaligned;
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io.cpu.resp_miss := load_miss;
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io.cpu.resp_miss := load_miss;
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// tag MSB distinguishes between loads destined for the PTW and CPU
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// tag MSB distinguishes between loads destined for the PTW and CPU
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io.cpu.resp_tag := Cat(r_req_ptw_load, r_cpu_req_type, r_cpu_req_idx(2,0), r_cpu_req_tag);
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io.cpu.resp_tag := Cat(r_req_ptw_load, r_cpu_req_type, r_cpu_req_idx(2,0), r_cpu_req_tag);
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