From 5f4b15b809888bd5f9b44cdadfcc0aa40c38688f Mon Sep 17 00:00:00 2001 From: Rimas Avizienis Date: Sun, 13 Nov 2011 00:03:17 -0800 Subject: [PATCH] added ld/st misaligned exceptions --- rocket/src/main/scala/cpu.scala | 3 ++- rocket/src/main/scala/ctrl.scala | 14 +++++++++----- rocket/src/main/scala/dcache.scala | 16 ++++++++++++---- 3 files changed, 23 insertions(+), 10 deletions(-) diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index 3e79bbfe..2e777f9f 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -85,7 +85,8 @@ class rocketProc extends Component ctrl.io.xcpt_dtlb_st := dtlb.io.cpu.xcpt_st; ctrl.io.dtlb_busy := dtlb.io.cpu.resp_busy; ctrl.io.dtlb_miss := dtlb.io.cpu.resp_miss; -// io.dmem.dtlb_miss := dtlb.io.cpu.resp_miss; + ctrl.io.xcpt_ma_ld := io.dmem.xcpt_ma_ld; + ctrl.io.xcpt_ma_st := io.dmem.xcpt_ma_st; // connect page table walker to TLBs, page table base register (from PCR) // and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 779b9328..c6fe2328 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -73,6 +73,8 @@ class ioCtrlAll extends Bundle() val xcpt_dtlb_ld = Bool('input); val xcpt_dtlb_st = Bool('input); val xcpt_itlb = Bool('input); + val xcpt_ma_ld = Bool('input); + val xcpt_ma_st = Bool('input); } class rocketCtrl extends Component @@ -381,6 +383,8 @@ class rocketCtrl extends Component // exception handling val mem_exception = + io.xcpt_ma_ld || + io.xcpt_ma_st || io.xcpt_dtlb_ld || io.xcpt_dtlb_st || mem_reg_xcpt_illegal || @@ -398,11 +402,11 @@ class rocketCtrl extends Component // interrupt Mux(mem_reg_xcpt_syscall, UFix(6,5), // system call // breakpoint - // misaligned load - // misaligned store - Mux(io.xcpt_dtlb_ld, UFix(8,5), // load fault - Mux(io.xcpt_dtlb_st, UFix(9,5), // store fault - UFix(0,5)))))))); // instruction address misaligned + Mux(io.xcpt_ma_ld, UFix(8,5), // misaligned load + Mux(io.xcpt_ma_st, UFix(9,5), // misaligned store + Mux(io.xcpt_dtlb_ld, UFix(10,5), // load fault + Mux(io.xcpt_dtlb_st, UFix(11,5), // store fault + UFix(0,5)))))))))); // instruction address misaligned // write cause to PCR on an exception io.dpath.exception := mem_exception; diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala index 8b4ce89e..fe2962d3 100644 --- a/rocket/src/main/scala/dcache.scala +++ b/rocket/src/main/scala/dcache.scala @@ -18,6 +18,8 @@ class ioDmem(view: List[String] = null) extends Bundle(view) { // val req_addr = UFix(PADDR_BITS, 'input); val req_data = Bits(64, 'input); val req_tag = Bits(5, 'input); + val xcpt_ma_ld = Bool('output); // misaligned load + val xcpt_ma_st = Bool('output); // misaligned store val resp_miss = Bool('output); val resp_val = Bool('output); val resp_data = Bits(64, 'output); @@ -151,16 +153,14 @@ class rocketDCacheDM_flush(lines: Int) extends Component { dcache.io.cpu.req_cmd := Mux(flushing, M_FLA, io.cpu.req_cmd); dcache.io.cpu.req_idx := Mux(flushing, Cat(flush_count, Bits(0,offsetbits)), io.cpu.req_idx); dcache.io.cpu.req_ppn := Mux(flushing, UFix(0,PPN_BITS), io.cpu.req_ppn); -// dcache.io.cpu.req_addr := -// Mux(flushing, Cat(Bits(0,tagmsb-taglsb+1), flush_count, Bits(0,offsetbits)).toUFix, -// io.cpu.req_addr); dcache.io.cpu.req_tag := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag); dcache.io.cpu.req_type := io.cpu.req_type; dcache.io.cpu.req_data ^^ io.cpu.req_data; -// dcache.io.cpu.dtlb_busy := io.cpu.dtlb_busy; dcache.io.cpu.dtlb_miss := io.cpu.dtlb_miss; dcache.io.mem ^^ io.mem; + io.cpu.xcpt_ma_ld := dcache.io.cpu.xcpt_ma_ld; + io.cpu.xcpt_ma_st := dcache.io.cpu.xcpt_ma_st; io.cpu.req_rdy := dcache.io.cpu.req_rdy && !flush_waiting; io.cpu.resp_miss := dcache.io.cpu.resp_miss; io.cpu.resp_data := dcache.io.cpu.resp_data; @@ -351,6 +351,14 @@ class rocketDCacheDM(lines: Int) extends Component { ((state === s_resolve_miss) && r_req_flush) || r_cpu_resp_val; + val misaligned = + ((r_cpu_req_type === MT_H) && r_cpu_req_idx(0).toBool) || + ((r_cpu_req_type === MT_W) && (r_cpu_req_idx(1,0) != Bits(0,2))) || + ((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0,3))); + + io.cpu.xcpt_ma_ld := r_cpu_req_val && r_req_load && misaligned; + io.cpu.xcpt_ma_st := r_cpu_req_val && r_req_store && misaligned; + io.cpu.resp_miss := load_miss; // tag MSB distinguishes between loads destined for the PTW and CPU io.cpu.resp_tag := Cat(r_req_ptw_load, r_cpu_req_type, r_cpu_req_idx(2,0), r_cpu_req_tag);