riscv/rocket-chip
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added ld/st misaligned exceptions

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This commit is contained in:
Rimas Avizienis
2011-11-13 00:03:17 -08:00
parent fbd44ea936
commit 5f4b15b809
3 changed files with 23 additions and 10 deletions
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3
rocket/src/main/scala/cpu.scala
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@ -85,7 +85,8 @@ class rocketProc extends Component
ctrl.io.xcpt_dtlb_st := dtlb.io.cpu.xcpt_st;
ctrl.io.dtlb_busy := dtlb.io.cpu.resp_busy;
ctrl.io.dtlb_miss := dtlb.io.cpu.resp_miss;
// io.dmem.dtlb_miss := dtlb.io.cpu.resp_miss;
ctrl.io.xcpt_ma_ld := io.dmem.xcpt_ma_ld;
ctrl.io.xcpt_ma_st := io.dmem.xcpt_ma_st;
// connect page table walker to TLBs, page table base register (from PCR)
// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)