From 5dbf9640e22629b78cd0bf076ad850e825fada44 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Fri, 22 Apr 2016 15:41:31 -0700 Subject: [PATCH] Use TLB flush signal to I$ explicitly --- rocket/src/main/scala/frontend.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/frontend.scala b/rocket/src/main/scala/frontend.scala index 490ae71c..5d67e158 100644 --- a/rocket/src/main/scala/frontend.scala +++ b/rocket/src/main/scala/frontend.scala @@ -106,7 +106,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa icache.io.req.bits.idx := io.cpu.npc icache.io.invalidate := io.cpu.flush_icache icache.io.s1_ppn := tlb.io.resp.ppn - icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.ptw.invalidate + icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.cpu.flush_tlb io.cpu.resp.valid := s2_valid && (s2_xcpt_if || s2_resp_valid) io.cpu.resp.bits.pc := s2_pc