riscv/rocket-chip
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lowercase SMI to Smi

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This commit is contained in:
Howard Mao 2016-01-11 16:18:38 -08:00
parent 9d2637c2c7
commit 5d7b5b219f
1 changed files with 28 additions and 28 deletions
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56
junctions/src/main/scala/smi.scala
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@ -3,35 +3,35 @@ package junctions
import Chisel._ import Chisel._
import cde.Parameters import cde.Parameters
class SMIReq(val dataWidth: Int, val addrWidth: Int) extends Bundle { class SmiReq(val dataWidth: Int, val addrWidth: Int) extends Bundle {
val rw = Bool() val rw = Bool()
val addr = UInt(width = addrWidth) val addr = UInt(width = addrWidth)
val data = Bits(width = dataWidth) val data = Bits(width = dataWidth)
override def cloneType = override def cloneType =
new SMIReq(dataWidth, addrWidth).asInstanceOf[this.type] new SmiReq(dataWidth, addrWidth).asInstanceOf[this.type]
} }
/** Simple Memory Interface IO. Used to communicate with PCR and SCR /** Simple Memory Interface IO. Used to communicate with PCR and SCR
* @param dataWidth the width in bits of the data field * @param dataWidth the width in bits of the data field
* @param addrWidth the width in bits of the addr field */ * @param addrWidth the width in bits of the addr field */
class SMIIO(val dataWidth: Int, val addrWidth: Int) extends Bundle { class SmiIO(val dataWidth: Int, val addrWidth: Int) extends Bundle {
val req = Decoupled(new SMIReq(dataWidth, addrWidth)) val req = Decoupled(new SmiReq(dataWidth, addrWidth))
val resp = Decoupled(Bits(width = dataWidth)).flip val resp = Decoupled(Bits(width = dataWidth)).flip
override def cloneType = override def cloneType =
new SMIIO(dataWidth, addrWidth).asInstanceOf[this.type] new SmiIO(dataWidth, addrWidth).asInstanceOf[this.type]
} }
abstract class SMIPeripheral extends Module { abstract class SmiPeripheral extends Module {
val dataWidth: Int val dataWidth: Int
val addrWidth: Int val addrWidth: Int
lazy val io = new SMIIO(dataWidth, addrWidth).flip lazy val io = new SmiIO(dataWidth, addrWidth).flip
} }
/** A simple sequential memory accessed through SMI */ /** A simple sequential memory accessed through Smi */
class SMIMem(val dataWidth: Int, val memDepth: Int) extends SMIPeripheral { class SmiMem(val dataWidth: Int, val memDepth: Int) extends SmiPeripheral {
// override // override
val addrWidth = log2Up(memDepth) val addrWidth = log2Up(memDepth)
@ -52,21 +52,21 @@ class SMIMem(val dataWidth: Int, val memDepth: Int) extends SMIPeripheral {
io.req.ready := !resp_valid io.req.ready := !resp_valid
} }
/** Arbitrate among several SMI clients /** Arbitrate among several Smi clients
* @param n the number of clients * @param n the number of clients
* @param dataWidth SMI data width * @param dataWidth Smi data width
* @param addrWidth SMI address width */ * @param addrWidth Smi address width */
class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int) class SmiArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
extends Module { extends Module {
val io = new Bundle { val io = new Bundle {
val in = Vec(new SMIIO(dataWidth, addrWidth), n).flip val in = Vec(new SmiIO(dataWidth, addrWidth), n).flip
val out = new SMIIO(dataWidth, addrWidth) val out = new SmiIO(dataWidth, addrWidth)
} }
val wait_resp = Reg(init = Bool(false)) val wait_resp = Reg(init = Bool(false))
val choice = Reg(UInt(width = log2Up(n))) val choice = Reg(UInt(width = log2Up(n)))
val req_arb = Module(new RRArbiter(new SMIReq(dataWidth, addrWidth), n)) val req_arb = Module(new RRArbiter(new SmiReq(dataWidth, addrWidth), n))
req_arb.io.in <> io.in.map(_.req) req_arb.io.in <> io.in.map(_.req)
req_arb.io.out.ready := io.out.req.ready && !wait_resp req_arb.io.out.ready := io.out.req.ready && !wait_resp
@ -88,12 +88,12 @@ class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
io.out.resp.ready := io.in(choice).resp.ready io.out.resp.ready := io.in(choice).resp.ready
} }
class SMIIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int) class SmiIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
(implicit p: Parameters) extends NastiModule()(p) { (implicit p: Parameters) extends NastiModule()(p) {
val io = new Bundle { val io = new Bundle {
val ar = Decoupled(new NastiReadAddressChannel).flip val ar = Decoupled(new NastiReadAddressChannel).flip
val r = Decoupled(new NastiReadDataChannel) val r = Decoupled(new NastiReadDataChannel)
val smi = new SMIIO(dataWidth, addrWidth) val smi = new SmiIO(dataWidth, addrWidth)
} }
private val maxWordsPerBeat = nastiXDataBits / dataWidth private val maxWordsPerBeat = nastiXDataBits / dataWidth
@ -170,13 +170,13 @@ class SMIIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
} }
} }
class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int) class SmiIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
(implicit p: Parameters) extends NastiModule()(p) { (implicit p: Parameters) extends NastiModule()(p) {
val io = new Bundle { val io = new Bundle {
val aw = Decoupled(new NastiWriteAddressChannel).flip val aw = Decoupled(new NastiWriteAddressChannel).flip
val w = Decoupled(new NastiWriteDataChannel).flip val w = Decoupled(new NastiWriteDataChannel).flip
val b = Decoupled(new NastiWriteResponseChannel) val b = Decoupled(new NastiWriteResponseChannel)
val smi = new SMIIO(dataWidth, addrWidth) val smi = new SmiIO(dataWidth, addrWidth)
} }
private val dataBytes = dataWidth / 8 private val dataBytes = dataWidth / 8
@ -185,7 +185,7 @@ class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
private val addrOffBits = addrWidth + byteOffBits private val addrOffBits = addrWidth + byteOffBits
assert(!io.aw.valid || io.aw.bits.size >= UInt(byteOffBits), assert(!io.aw.valid || io.aw.bits.size >= UInt(byteOffBits),
"Nasti size must be >= SMI size") "Nasti size must be >= Smi size")
val id = Reg(UInt(width = nastiWIdBits)) val id = Reg(UInt(width = nastiWIdBits))
val addr = Reg(UInt(width = addrWidth)) val addr = Reg(UInt(width = addrWidth))
@ -251,26 +251,26 @@ class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
when (io.b.fire()) { state := s_idle } when (io.b.fire()) { state := s_idle }
} }
/** Convert Nasti protocol to SMI protocol */ /** Convert Nasti protocol to Smi protocol */
class SMIIONastiIOConverter(val dataWidth: Int, val addrWidth: Int) class SmiIONastiIOConverter(val dataWidth: Int, val addrWidth: Int)
(implicit p: Parameters) extends NastiModule()(p) { (implicit p: Parameters) extends NastiModule()(p) {
val io = new Bundle { val io = new Bundle {
val nasti = (new NastiIO).flip val nasti = (new NastiIO).flip
val smi = new SMIIO(dataWidth, addrWidth) val smi = new SmiIO(dataWidth, addrWidth)
} }
require(isPow2(dataWidth), "SMI data width must be power of 2") require(isPow2(dataWidth), "Smi data width must be power of 2")
val reader = Module(new SMIIONastiReadIOConverter(dataWidth, addrWidth)) val reader = Module(new SmiIONastiReadIOConverter(dataWidth, addrWidth))
reader.io.ar <> io.nasti.ar reader.io.ar <> io.nasti.ar
io.nasti.r <> reader.io.r io.nasti.r <> reader.io.r
val writer = Module(new SMIIONastiWriteIOConverter(dataWidth, addrWidth)) val writer = Module(new SmiIONastiWriteIOConverter(dataWidth, addrWidth))
writer.io.aw <> io.nasti.aw writer.io.aw <> io.nasti.aw
writer.io.w <> io.nasti.w writer.io.w <> io.nasti.w
io.nasti.b <> writer.io.b io.nasti.b <> writer.io.b
val arb = Module(new SMIArbiter(2, dataWidth, addrWidth)) val arb = Module(new SmiArbiter(2, dataWidth, addrWidth))
arb.io.in(0) <> reader.io.smi arb.io.in(0) <> reader.io.smi
arb.io.in(1) <> writer.io.smi arb.io.in(1) <> writer.io.smi
io.smi <> arb.io.out io.smi <> arb.io.out