From 5d7b5b219f6be834980e0d34aa29a1cbd0feee3e Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 11 Jan 2016 16:18:38 -0800 Subject: [PATCH] lowercase SMI to Smi --- junctions/src/main/scala/smi.scala | 56 +++++++++++++++--------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/junctions/src/main/scala/smi.scala b/junctions/src/main/scala/smi.scala index 96616b1e..c7e27af2 100644 --- a/junctions/src/main/scala/smi.scala +++ b/junctions/src/main/scala/smi.scala @@ -3,35 +3,35 @@ package junctions import Chisel._ import cde.Parameters -class SMIReq(val dataWidth: Int, val addrWidth: Int) extends Bundle { +class SmiReq(val dataWidth: Int, val addrWidth: Int) extends Bundle { val rw = Bool() val addr = UInt(width = addrWidth) val data = Bits(width = dataWidth) override def cloneType = - new SMIReq(dataWidth, addrWidth).asInstanceOf[this.type] + new SmiReq(dataWidth, addrWidth).asInstanceOf[this.type] } /** Simple Memory Interface IO. Used to communicate with PCR and SCR * @param dataWidth the width in bits of the data field * @param addrWidth the width in bits of the addr field */ -class SMIIO(val dataWidth: Int, val addrWidth: Int) extends Bundle { - val req = Decoupled(new SMIReq(dataWidth, addrWidth)) +class SmiIO(val dataWidth: Int, val addrWidth: Int) extends Bundle { + val req = Decoupled(new SmiReq(dataWidth, addrWidth)) val resp = Decoupled(Bits(width = dataWidth)).flip override def cloneType = - new SMIIO(dataWidth, addrWidth).asInstanceOf[this.type] + new SmiIO(dataWidth, addrWidth).asInstanceOf[this.type] } -abstract class SMIPeripheral extends Module { +abstract class SmiPeripheral extends Module { val dataWidth: Int val addrWidth: Int - lazy val io = new SMIIO(dataWidth, addrWidth).flip + lazy val io = new SmiIO(dataWidth, addrWidth).flip } -/** A simple sequential memory accessed through SMI */ -class SMIMem(val dataWidth: Int, val memDepth: Int) extends SMIPeripheral { +/** A simple sequential memory accessed through Smi */ +class SmiMem(val dataWidth: Int, val memDepth: Int) extends SmiPeripheral { // override val addrWidth = log2Up(memDepth) @@ -52,21 +52,21 @@ class SMIMem(val dataWidth: Int, val memDepth: Int) extends SMIPeripheral { io.req.ready := !resp_valid } -/** Arbitrate among several SMI clients +/** Arbitrate among several Smi clients * @param n the number of clients - * @param dataWidth SMI data width - * @param addrWidth SMI address width */ -class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int) + * @param dataWidth Smi data width + * @param addrWidth Smi address width */ +class SmiArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int) extends Module { val io = new Bundle { - val in = Vec(new SMIIO(dataWidth, addrWidth), n).flip - val out = new SMIIO(dataWidth, addrWidth) + val in = Vec(new SmiIO(dataWidth, addrWidth), n).flip + val out = new SmiIO(dataWidth, addrWidth) } val wait_resp = Reg(init = Bool(false)) val choice = Reg(UInt(width = log2Up(n))) - val req_arb = Module(new RRArbiter(new SMIReq(dataWidth, addrWidth), n)) + val req_arb = Module(new RRArbiter(new SmiReq(dataWidth, addrWidth), n)) req_arb.io.in <> io.in.map(_.req) req_arb.io.out.ready := io.out.req.ready && !wait_resp @@ -88,12 +88,12 @@ class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int) io.out.resp.ready := io.in(choice).resp.ready } -class SMIIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int) +class SmiIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int) (implicit p: Parameters) extends NastiModule()(p) { val io = new Bundle { val ar = Decoupled(new NastiReadAddressChannel).flip val r = Decoupled(new NastiReadDataChannel) - val smi = new SMIIO(dataWidth, addrWidth) + val smi = new SmiIO(dataWidth, addrWidth) } private val maxWordsPerBeat = nastiXDataBits / dataWidth @@ -170,13 +170,13 @@ class SMIIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int) } } -class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int) +class SmiIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int) (implicit p: Parameters) extends NastiModule()(p) { val io = new Bundle { val aw = Decoupled(new NastiWriteAddressChannel).flip val w = Decoupled(new NastiWriteDataChannel).flip val b = Decoupled(new NastiWriteResponseChannel) - val smi = new SMIIO(dataWidth, addrWidth) + val smi = new SmiIO(dataWidth, addrWidth) } private val dataBytes = dataWidth / 8 @@ -185,7 +185,7 @@ class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int) private val addrOffBits = addrWidth + byteOffBits assert(!io.aw.valid || io.aw.bits.size >= UInt(byteOffBits), - "Nasti size must be >= SMI size") + "Nasti size must be >= Smi size") val id = Reg(UInt(width = nastiWIdBits)) val addr = Reg(UInt(width = addrWidth)) @@ -251,26 +251,26 @@ class SMIIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int) when (io.b.fire()) { state := s_idle } } -/** Convert Nasti protocol to SMI protocol */ -class SMIIONastiIOConverter(val dataWidth: Int, val addrWidth: Int) +/** Convert Nasti protocol to Smi protocol */ +class SmiIONastiIOConverter(val dataWidth: Int, val addrWidth: Int) (implicit p: Parameters) extends NastiModule()(p) { val io = new Bundle { val nasti = (new NastiIO).flip - val smi = new SMIIO(dataWidth, addrWidth) + val smi = new SmiIO(dataWidth, addrWidth) } - require(isPow2(dataWidth), "SMI data width must be power of 2") + require(isPow2(dataWidth), "Smi data width must be power of 2") - val reader = Module(new SMIIONastiReadIOConverter(dataWidth, addrWidth)) + val reader = Module(new SmiIONastiReadIOConverter(dataWidth, addrWidth)) reader.io.ar <> io.nasti.ar io.nasti.r <> reader.io.r - val writer = Module(new SMIIONastiWriteIOConverter(dataWidth, addrWidth)) + val writer = Module(new SmiIONastiWriteIOConverter(dataWidth, addrWidth)) writer.io.aw <> io.nasti.aw writer.io.w <> io.nasti.w io.nasti.b <> writer.io.b - val arb = Module(new SMIArbiter(2, dataWidth, addrWidth)) + val arb = Module(new SmiArbiter(2, dataWidth, addrWidth)) arb.io.in(0) <> reader.io.smi arb.io.in(1) <> writer.io.smi io.smi <> arb.io.out