From 5d5b5a66f4d9600ffb3c5b3c4a1206722d591026 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 12 Oct 2016 21:02:01 -0700 Subject: [PATCH] tilelink2 RAMModel: fix a write-bad-data bug --- src/main/scala/uncore/tilelink2/RAMModel.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/uncore/tilelink2/RAMModel.scala b/src/main/scala/uncore/tilelink2/RAMModel.scala index 2ee1d607..bb560da7 100644 --- a/src/main/scala/uncore/tilelink2/RAMModel.scala +++ b/src/main/scala/uncore/tilelink2/RAMModel.scala @@ -103,7 +103,7 @@ class TLRAMModel(log: String = "") extends LazyModule a_flight.size := edge.size(in.a.bits) a_flight.opcode := in.a.bits.opcode - flight(in.a.bits.source) := a_flight + when (in.a.fire()) { flight(in.a.bits.source) := a_flight } val bypass = if (edge.manager.minLatency > 0) Bool(false) else in.a.valid && in.a.bits.source === out.d.bits.source val d_flight = RegNext(Mux(bypass, a_flight, flight(out.d.bits.source)))