riscv/rocket-chip
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Merge pull request #1019 from freechipsproject/move-rocket-int-sync

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Move rocket output interrupt syncronizers
This commit is contained in:
Henry Cook 2017-09-27 14:46:02 -07:00 committed by GitHub
commit 5d08b37dab
2 changed files with 6 additions and 6 deletions
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6
src/main/scala/coreplex/RocketCoreplex.scala
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@ -84,7 +84,11 @@ trait HasRocketTiles extends HasSystemBus
lip.foreach { coreIntXbar.intnode := _ } // lip
wrapper.coreIntNode := coreIntXbar.intnode
wrapper.intOutputNode.foreach { plic.intnode := _ }
wrapper.intOutputNode.foreach { case int =>
val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency))
rocketIntXing.intnode := int
plic.intnode := rocketIntXing.intnode
}
wrapper
}

6
src/main/scala/tile/RocketTile.scala
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@ -213,11 +213,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
def outputInterruptXingLatency: Int
rocket.intOutputNode.foreach { rocketIntOutputNode =>
val outXing = LazyModule(new IntXing(outputInterruptXingLatency))
intOutputNode.get := outXing.intnode
outXing.intnode := rocketIntOutputNode
}
intOutputNode.foreach { _ := rocket.intOutputNode.get }
lazy val module = new LazyModuleImp(this) {
val io = new CoreBundle