From 1fda05970a5934a3a3494e03fd78f31ca7a6ddcd Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 27 Sep 2017 12:02:04 -0700 Subject: [PATCH 1/2] rocket: move interrupt synchronizers to correct side of crossing --- src/main/scala/coreplex/RocketCoreplex.scala | 6 +++++- src/main/scala/tile/RocketTile.scala | 6 ------ 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index 6bac3fd4..52c84473 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -84,7 +84,11 @@ trait HasRocketTiles extends HasSystemBus lip.foreach { coreIntXbar.intnode := _ } // lip wrapper.coreIntNode := coreIntXbar.intnode - wrapper.intOutputNode.foreach { plic.intnode := _ } + wrapper.intOutputNode.foreach { case int => + val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency)) + rocketIntXing.intnode := int + plic.intnode := rocketIntXing.intnode + } wrapper } diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index caa6f1a1..0e83eb3c 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -213,12 +213,6 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: def outputInterruptXingLatency: Int - rocket.intOutputNode.foreach { rocketIntOutputNode => - val outXing = LazyModule(new IntXing(outputInterruptXingLatency)) - intOutputNode.get := outXing.intnode - outXing.intnode := rocketIntOutputNode - } - lazy val module = new LazyModuleImp(this) { val io = new CoreBundle with HasExternallyDrivenTileConstants From f48bf2ac2f36990e876ba15b0db8f3226901d2ef Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 27 Sep 2017 12:53:19 -0700 Subject: [PATCH 2/2] rocket: connect uncrossed output interrupts --- src/main/scala/tile/RocketTile.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 0e83eb3c..376a2620 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -213,6 +213,8 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: def outputInterruptXingLatency: Int + intOutputNode.foreach { _ := rocket.intOutputNode.get } + lazy val module = new LazyModuleImp(this) { val io = new CoreBundle with HasExternallyDrivenTileConstants