diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala
index 6bac3fd4..52c84473 100644
--- a/src/main/scala/coreplex/RocketCoreplex.scala
+++ b/src/main/scala/coreplex/RocketCoreplex.scala
@@ -84,7 +84,11 @@ trait HasRocketTiles extends HasSystemBus
     lip.foreach { coreIntXbar.intnode := _ }                // lip
     wrapper.coreIntNode   := coreIntXbar.intnode
 
-    wrapper.intOutputNode.foreach { plic.intnode := _ }
+    wrapper.intOutputNode.foreach { case int =>
+      val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency))
+      rocketIntXing.intnode := int
+      plic.intnode := rocketIntXing.intnode
+    }
 
     wrapper
   }
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index caa6f1a1..376a2620 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -213,11 +213,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
 
   def outputInterruptXingLatency: Int
 
-  rocket.intOutputNode.foreach { rocketIntOutputNode =>
-    val outXing = LazyModule(new IntXing(outputInterruptXingLatency))
-    intOutputNode.get := outXing.intnode
-    outXing.intnode := rocketIntOutputNode
-  }
+  intOutputNode.foreach { _ := rocket.intOutputNode.get }
 
   lazy val module = new LazyModuleImp(this) {
     val io = new CoreBundle