riscv/rocket-chip
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Don't report a TL error if overwriting a whole ITIM word

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Andrew Waterman 2017-11-08 16:46:57 -08:00 committed by Wesley W. Terpstra
parent 9b16d25861
commit 5c1b34d854
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/ICache.scala
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@ -313,7 +313,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
} }
respValid := s2_slaveValid || (respValid && !tl.d.ready) respValid := s2_slaveValid || (respValid && !tl.d.ready)
val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable, s2_slaveValid) val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !(edge_in.get.hasData(s1_a) && s1_a.mask.andR), s2_slaveValid)
when (s2_slaveValid) { when (s2_slaveValid) {
when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true } when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true }
def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i)) def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i))