From 5c1b34d854526581a9eb68a76f434b7e6e0dd7fb Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 8 Nov 2017 16:46:57 -0800 Subject: [PATCH] Don't report a TL error if overwriting a whole ITIM word --- src/main/scala/rocket/ICache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index cc998775..82ca13d4 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -313,7 +313,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) } respValid := s2_slaveValid || (respValid && !tl.d.ready) - val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable, s2_slaveValid) + val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !(edge_in.get.hasData(s1_a) && s1_a.mask.andR), s2_slaveValid) when (s2_slaveValid) { when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true } def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i))