riscv/rocket-chip
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Don't use clone

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This commit is contained in:
Andrew Waterman
2015-07-15 17:30:50 -07:00
parent be2ff6dec7
commit 5b7f3c3006
5 changed files with 8 additions and 8 deletions
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rocket/src/main/scala/icache.scala
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@@ -55,7 +55,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
val s2_valid = Reg(init=Bool(true))
val s2_pc = Reg(init=UInt(START_ADDR))
val s2_btb_resp_valid = Reg(init=Bool(false))
val s2_btb_resp_bits = Reg(btb.io.resp.bits.clone)
val s2_btb_resp_bits = Reg(btb.io.resp.bits)
val s2_xcpt_if = Reg(init=Bool(false))
val msb = vaddrBits-1