diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index d50c1103..991ed4b5 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -367,7 +367,7 @@ class Control extends CoreModule
   val ex_reg_xcpt_interrupt  = Reg(Bool())
   val ex_reg_valid           = Reg(Bool())
   val ex_reg_btb_hit         = Reg(Bool())
-  val ex_reg_btb_resp        = Reg(io.imem.btb_resp.bits.clone)
+  val ex_reg_btb_resp        = Reg(io.imem.btb_resp.bits)
   val ex_reg_xcpt            = Reg(Bool())
   val ex_reg_flush_pipe      = Reg(Bool())
   val ex_reg_load_use        = Reg(Bool())
@@ -376,7 +376,7 @@ class Control extends CoreModule
   val mem_reg_xcpt_interrupt  = Reg(Bool())
   val mem_reg_valid           = Reg(Bool())
   val mem_reg_btb_hit         = Reg(Bool())
-  val mem_reg_btb_resp        = Reg(io.imem.btb_resp.bits.clone)
+  val mem_reg_btb_resp        = Reg(io.imem.btb_resp.bits)
   val mem_reg_xcpt            = Reg(Bool())
   val mem_reg_replay          = Reg(Bool())
   val mem_reg_flush_pipe      = Reg(Bool())
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 43a30ef5..59fc041c 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -55,7 +55,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
   val s2_valid = Reg(init=Bool(true))
   val s2_pc = Reg(init=UInt(START_ADDR))
   val s2_btb_resp_valid = Reg(init=Bool(false))
-  val s2_btb_resp_bits = Reg(btb.io.resp.bits.clone)
+  val s2_btb_resp_bits = Reg(btb.io.resp.bits)
   val s2_xcpt_if = Reg(init=Bool(false))
 
   val msb = vaddrBits-1
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 0ad6f301..9c822d50 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -602,19 +602,19 @@ class HellaCache extends L1HellaCacheModule {
 
   io.cpu.req.ready := Bool(true)
   val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false))
-  val s1_req = Reg(io.cpu.req.bits.clone)
+  val s1_req = Reg(io.cpu.req.bits)
   val s1_valid_masked = s1_valid && !io.cpu.req.bits.kill
   val s1_replay = Reg(init=Bool(false))
   val s1_clk_en = Reg(Bool())
 
   val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
-  val s2_req = Reg(io.cpu.req.bits.clone)
+  val s2_req = Reg(io.cpu.req.bits)
   val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
   val s2_recycle = Bool()
   val s2_valid_masked = Bool()
 
   val s3_valid = Reg(init=Bool(false))
-  val s3_req = Reg(io.cpu.req.bits.clone)
+  val s3_req = Reg(io.cpu.req.bits)
   val s3_way = Reg(Bits())
 
   val s1_recycled = RegEnable(s2_recycle, Bool(false), s1_clk_en)
diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index c8838c69..61a4b000 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -62,7 +62,7 @@ class AccumulatorExample extends RoCC
 {
   val n = 4
   val regfile = Mem(UInt(width = xLen), n)
-  val busy = Reg(init=Vec.fill(n){Bool(false)})
+  val busy = Reg(init=Vec(Bool(false), n))
 
   val cmd = Queue(io.cmd)
   val funct = cmd.bits.inst.funct
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index adb64960..a5d87943 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -109,7 +109,7 @@ class TLB extends TLBModule {
   val r_req = Reg(new TLBReq)
 
   val tag_cam = Module(new RocketCAM)
-  val tag_ram = Mem(io.ptw.resp.bits.pte.ppn.clone, entries)
+  val tag_ram = Mem(io.ptw.resp.bits.pte.ppn, entries)
   
   val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
   tag_cam.io.tag := lookup_tag