NastiTest should cycle through write ids
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@ -44,7 +44,7 @@ class NastiGenerator(id: Int)(implicit val p: Parameters) extends Module
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io.mem.aw.valid := (state === s_write_addr)
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io.mem.aw.valid := (state === s_write_addr)
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io.mem.aw.bits := NastiWriteAddressChannel(
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io.mem.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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id = write_idx(nastiXIdBits - 1, 0),
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addr = write_addr,
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addr = write_addr,
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len = UInt(0),
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len = UInt(0),
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size = UInt(log2Ceil(genWordBytes)))
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size = UInt(log2Ceil(genWordBytes)))
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