riscv/rocket-chip
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Generate D$ replay_next signals correctly

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Andrew Waterman
2014-01-16 00:16:09 -08:00
parent 6ebdc4d94e
commit 57f4d89c90
3 changed files with 9 additions and 4 deletions
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2
rocket/src/main/scala/ctrl.scala
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@@ -538,7 +538,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
(mem_reg_mem_val && io.dmem.xcpt.pf.ld, UInt(10)),
(mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(11))))
val dcache_kill_mem = mem_reg_wen && io.dmem.resp.bits.load_replay_next // structural hazard on writeback port
val dcache_kill_mem = mem_reg_wen && io.dmem.replay_next.valid // structural hazard on writeback port
val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem
val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid