diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index a87fcf01..48ea127e 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -44,6 +44,9 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Modu
     resp.bits.tag := io.mem.resp.bits.tag >> UInt(log2Up(n))
     resp.bits.nack := io.mem.resp.bits.nack && tag_hit
     resp.bits.replay := io.mem.resp.bits.replay && tag_hit
-    resp.bits.load_replay_next := io.mem.resp.bits.load_replay_next && tag_hit
+
+    io.requestor(i).replay_next.valid := io.mem.replay_next.valid &&
+      io.mem.replay_next.bits(log2Up(n)-1,0) === UInt(log2Up(n))
+    io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> UInt(log2Up(n))
   }
 }
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 7ffb0623..f7f41a94 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -538,7 +538,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
     (mem_reg_mem_val && io.dmem.xcpt.pf.ld,  UInt(10)),
     (mem_reg_mem_val && io.dmem.xcpt.pf.st,  UInt(11))))
 
-  val dcache_kill_mem = mem_reg_wen && io.dmem.resp.bits.load_replay_next // structural hazard on writeback port
+  val dcache_kill_mem = mem_reg_wen && io.dmem.replay_next.valid // structural hazard on writeback port
   val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
   val replay_mem  = dcache_kill_mem || mem_reg_replay || fpu_kill_mem
   val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 6e5c471a..ba08110c 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -697,7 +697,6 @@ class HellaCacheReq(implicit val conf: DCacheConfig) extends DCacheBundle {
 class HellaCacheResp(implicit val conf: DCacheConfig) extends DCacheBundle {
   val nack = Bool() // comes 2 cycles after req.fire
   val replay = Bool()
-  val load_replay_next = Bool() // next cycle, replay and has_data will be true
   val typ = Bits(width = 3)
   val has_data = Bool()
   val data = Bits(width = conf.databits)
@@ -722,6 +721,7 @@ class HellaCacheExceptions extends Bundle {
 class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle {
   val req = Decoupled(new HellaCacheReq)
   val resp = Valid(new HellaCacheResp).flip
+  val replay_next = Valid(Bits(width = conf.reqtagbits)).flip
   val xcpt = (new HellaCacheExceptions).asInput
   val ptw = (new TLBPTWIO).flip
   val ordered = Bool(INPUT)
@@ -1034,13 +1034,15 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
   io.cpu.resp.bits.nack := s2_valid && s2_nack
   io.cpu.resp.bits := s2_req
   io.cpu.resp.bits.has_data := isRead(s2_req.cmd) || s2_sc
-  io.cpu.resp.bits.load_replay_next := s1_replay && (s1_read || s1_sc)
   io.cpu.resp.bits.replay := s2_replay
   io.cpu.resp.bits.data := loadgen.word
   io.cpu.resp.bits.data_subword := loadgen.byte | s2_sc_fail
   io.cpu.resp.bits.store_data := s2_req.data
   io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
 
+  io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc)
+  io.cpu.replay_next.bits := s1_req.tag
+
   io.mem.grant_ack <> mshrs.io.mem_finish
 }