From 88332bd8852dc21002df412cacded529449c7d36 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Sun, 13 Aug 2017 15:20:47 -0700 Subject: [PATCH] max-core-cycles: Add a +max-core-cycles PlusArg --- src/main/scala/rocket/RocketCore.scala | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index 55338708..15d2ac6e 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -702,6 +702,13 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) wb_reg_cinst, wb_reg_cinst) } + val max_core_cycles = PlusArg("max-core-cycles", + default = 0, + docstring = "Maximum Core Clock cycles simulation may run before timeout. Ignored if 0 (Default).") + when (max_core_cycles > UInt(0)) { + assert (csr.io.time < max_core_cycles, "Maximum Core Cycles reached.") + } + def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_||_), PriorityMux(x))