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Fix Fragmenter to ensure logical operations must be sent out atomically.

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Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
This commit is contained in:
Jacob Chang 2016-12-07 16:22:05 -08:00
parent 9ac78a0d37
commit 54cc071a64
2 changed files with 20 additions and 10 deletions
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2
src/main/scala/uncore/tilelink2/Fragmenter.scala
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@ -31,7 +31,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
TransferSizes.none
def mapManager(m: TLManagerParameters) = m.copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = expandTransfer(m.supportsLogical),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet),
supportsPutFull = expandTransfer(m.supportsPutFull),
supportsPutPartial = expandTransfer(m.supportsPutPartial),

14
src/main/scala/uncore/tilelink2/Fuzzer.scala
View File

@ -108,9 +108,13 @@ class TLFuzzer(
val dataBits = edge.bundle.dataBits
// Progress through operations
val num_reqs = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
val num_resps = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
val num_reqs = Reg(init = UInt(nOperations, log2Up(nOperations)))
val num_resps = Reg(init = UInt(nOperations, log2Up(nOperations)))
if (nOperations>0) {
io.finished := num_resps === UInt(0)
} else {
io.finished := Bool(false)
}
// Progress within each operation
val a = out.a.bits
@ -179,7 +183,11 @@ class TLFuzzer(
UInt("b101") -> hbits))
// Wire both the used and un-used channel signals
if (nOperations>0) {
out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0)
} else {
out.a.valid := legal && alloc.valid
}
out.a.bits := bits
out.b.ready := Bool(true)
out.c.valid := Bool(false)
@ -190,6 +198,7 @@ class TLFuzzer(
inc := !legal || req_done
inc_beat := !legal || out.a.fire()
if (nOperations>0) {
when (out.a.fire() && a_last) {
num_reqs := num_reqs - UInt(1)
}
@ -199,6 +208,7 @@ class TLFuzzer(
}
}
}
}
/** Synthesizeable integration test */
import unittest._