From 54cc071a64bddaec065dbee7fae9b1a69bc8bf8c Mon Sep 17 00:00:00 2001
From: Jacob Chang <jchang@.sifive.com>
Date: Wed, 7 Dec 2016 16:22:05 -0800
Subject: [PATCH] Fix Fragmenter to ensure logical operations must be sent out
 atomically.

Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
---
 .../scala/uncore/tilelink2/Fragmenter.scala   |  2 +-
 src/main/scala/uncore/tilelink2/Fuzzer.scala  | 28 +++++++++++++------
 2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala
index 21817bb1..1c95c78e 100644
--- a/src/main/scala/uncore/tilelink2/Fragmenter.scala
+++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala
@@ -31,7 +31,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
     TransferSizes.none
   def mapManager(m: TLManagerParameters) = m.copy(
     supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
-    supportsLogical    = expandTransfer(m.supportsLogical),
+    supportsLogical    = shrinkTransfer(m.supportsLogical),
     supportsGet        = expandTransfer(m.supportsGet),
     supportsPutFull    = expandTransfer(m.supportsPutFull),
     supportsPutPartial = expandTransfer(m.supportsPutPartial),
diff --git a/src/main/scala/uncore/tilelink2/Fuzzer.scala b/src/main/scala/uncore/tilelink2/Fuzzer.scala
index 38756238..9122545f 100644
--- a/src/main/scala/uncore/tilelink2/Fuzzer.scala
+++ b/src/main/scala/uncore/tilelink2/Fuzzer.scala
@@ -108,9 +108,13 @@ class TLFuzzer(
     val dataBits     = edge.bundle.dataBits
 
     // Progress through operations
-    val num_reqs = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
-    val num_resps = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
-    io.finished  := num_resps === UInt(0)
+    val num_reqs = Reg(init = UInt(nOperations, log2Up(nOperations)))
+    val num_resps = Reg(init = UInt(nOperations, log2Up(nOperations)))
+    if (nOperations>0) {
+      io.finished  := num_resps === UInt(0)
+    } else {
+      io.finished := Bool(false)
+    }
 
     // Progress within each operation
     val a = out.a.bits
@@ -179,7 +183,11 @@ class TLFuzzer(
       UInt("b101") -> hbits))
 
     // Wire both the used and un-used channel signals
-    out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0)
+    if (nOperations>0) {
+      out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0)
+    } else {
+      out.a.valid := legal && alloc.valid
+    }
     out.a.bits  := bits
     out.b.ready := Bool(true)
     out.c.valid := Bool(false)
@@ -190,12 +198,14 @@ class TLFuzzer(
     inc := !legal || req_done
     inc_beat := !legal || out.a.fire()
 
-    when (out.a.fire() && a_last) {
-      num_reqs := num_reqs - UInt(1)
-    }
+    if (nOperations>0) {
+      when (out.a.fire() && a_last) {
+        num_reqs := num_reqs - UInt(1)
+      }
 
-    when (out.d.fire() && d_last) {
-      num_resps := num_resps - UInt(1)
+      when (out.d.fire() && d_last) {
+        num_resps := num_resps - UInt(1)
+      }
     }
   }
 }