riscv/rocket-chip
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add fp loads/stores

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This commit is contained in:
Andrew Waterman 2012-02-07 23:54:25 -08:00
parent 1be9d15944
commit 5403d069e9
7 changed files with 319 additions and 173 deletions
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14
rocket/src/main/scala/consts.scala
View File

@ -77,9 +77,6 @@ object Constants
val Y = UFix(1, 1);
val Y_SH = UFix(1, 1);
// val FPU_N = UFix(0, 1);
// val FPU_Y = FPU_N;
val FWBQ_N = UFix(0, 1);
val FWBQ_Y = UFix(1, 1);
@ -180,7 +177,7 @@ object Constants
// rocketNBDCacheDM parameters
val CPU_DATA_BITS = 64;
val CPU_TAG_BITS = 5;
val CPU_TAG_BITS = 6;
val DCACHE_TAG_BITS = 1 + CPU_TAG_BITS;
val OFFSET_BITS = 6; // log2(cache line size in bytes)
val NMSHR = 2; // number of primary misses
@ -209,9 +206,12 @@ object Constants
val START_ADDR = 0x2000;
val HAVE_RVC = Bool(false);
val HAVE_FPU = Bool(false);
val HAVE_VEC = Bool(false);
val HAVE_RVC = false
val HAVE_FPU = true
val HAVE_VEC = false
val FPU_N = UFix(0, 1);
val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N;
}
}

9
rocket/src/main/scala/cpu.scala
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@ -111,6 +111,15 @@ class rocketProc extends Component
io.console.bits := dpath.io.console.bits;
io.console.valid := dpath.io.console.valid;
ctrl.io.console.rdy := io.console.rdy;
if (HAVE_FPU)
{
val fpu = new rocketFPU
fpu.io.dmem.resp_val := arb.io.cpu.resp_val;
fpu.io.dmem.resp_tag := arb.io.cpu.resp_tag;
fpu.io.dmem.resp_data := arb.io.cpu.resp_data;
dpath.io.fpu <> fpu.io.dpath
}
}
}

264
rocket/src/main/scala/ctrl.scala
View File

@ -37,7 +37,10 @@ class ioCtrlDpath extends Bundle()
val id_eret = Bool(OUTPUT);
val wb_eret = Bool(OUTPUT);
val mem_load = Bool(OUTPUT);
val wen = Bool(OUTPUT);
val ex_fp_val= Bool(OUTPUT);
val ex_wen = Bool(OUTPUT);
val mem_wen = Bool(OUTPUT);
val wb_wen = Bool(OUTPUT);
// instruction in execute is an unconditional jump
val ex_jmp = Bool(OUTPUT);
val ex_jr = Bool(OUTPUT);
@ -60,12 +63,15 @@ class ioCtrlDpath extends Bundle()
val div_result_val = Bool(INPUT);
val mul_rdy = Bool(INPUT);
val mul_result_val = Bool(INPUT);
val mem_wb = Bool(INPUT);
val ex_waddr = UFix(5,INPUT); // write addr from execute stage
val mem_waddr = UFix(5,INPUT); // write addr from memory stage
val wb_waddr = UFix(5,INPUT); // write addr from writeback stage
val status = Bits(17, INPUT);
val sboard_clr = Bool(INPUT);
val sboard_clra = UFix(5, INPUT);
val fp_sboard_clr = Bool(INPUT);
val fp_sboard_clra = UFix(5, INPUT);
val mem_valid = Bool(INPUT); // high if there's a valid (not flushed) instruction in mem stage
val irq_timer = Bool(INPUT);
val irq_ipi = Bool(INPUT);
@ -76,7 +82,7 @@ class ioCtrlAll extends Bundle()
val dpath = new ioCtrlDpath();
val console = new ioConsole(List("rdy"));
val imem = new ioImem(List("req_val", "resp_val")).flip();
val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_replay", "resp_nack")).flip();
val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack")).flip();
val dtlb_val = Bool(OUTPUT);
val dtlb_kill = Bool(OUTPUT);
val dtlb_rdy = Bool(INPUT);
@ -93,76 +99,8 @@ class rocketCtrl extends Component
{
val io = new ioCtrlAll();
// val fp =
// ListLookup(io.dpath.inst,
// List(Bool(false)),
// Array(
// FMOVZ -> List(Bool(true)),
// FMOVN -> List(Bool(true)),
// FADD_S -> List(Bool(true)),
// FSUB_S -> List(Bool(true)),
// FMUL_S -> List(Bool(true)),
// FDIV_S -> List(Bool(true)),
// FSQRT_S -> List(Bool(true)),
// FSGNJ_S -> List(Bool(true)),
// FSGNJN_S -> List(Bool(true)),
// FSGNJX_S -> List(Bool(true)),
// FADD_D -> List(Bool(true)),
// FSUB_D -> List(Bool(true)),
// FMUL_D -> List(Bool(true)),
// FDIV_D -> List(Bool(true)),
// FSQRT_D -> List(Bool(true)),
// FSGNJ_D -> List(Bool(true)),
// FSGNJN_D -> List(Bool(true)),
// FSGNJX_D -> List(Bool(true)),
// FCVT_L_S -> List(Bool(true)),
// FCVT_LU_S -> List(Bool(true)),
// FCVT_W_S -> List(Bool(true)),
// FCVT_WU_S -> List(Bool(true)),
// FCVT_L_D -> List(Bool(true)),
// FCVT_LU_D -> List(Bool(true)),
// FCVT_W_D -> List(Bool(true)),
// FCVT_WU_D -> List(Bool(true)),
// FCVT_S_L -> List(Bool(true)),
// FCVT_S_LU -> List(Bool(true)),
// FCVT_S_W -> List(Bool(true)),
// FCVT_S_WU -> List(Bool(true)),
// FCVT_D_L -> List(Bool(true)),
// FCVT_D_LU -> List(Bool(true)),
// FCVT_D_W -> List(Bool(true)),
// FCVT_D_WU -> List(Bool(true)),
// FCVT_S_D -> List(Bool(true)),
// FCVT_D_S -> List(Bool(true)),
// FEQ_S -> List(Bool(true)),
// FLT_S -> List(Bool(true)),
// FLE_S -> List(Bool(true)),
// FEQ_D -> List(Bool(true)),
// FLT_D -> List(Bool(true)),
// FLE_D -> List(Bool(true)),
// FMIN_S -> List(Bool(true)),
// FMAX_S -> List(Bool(true)),
// FMIN_D -> List(Bool(true)),
// FMAX_D -> List(Bool(true)),
// MFTX_S -> List(Bool(true)),
// MFTX_D -> List(Bool(true)),
// MFFSR -> List(Bool(true)),
// MXTF_S -> List(Bool(true)),
// MXTF_D -> List(Bool(true)),
// MTFSR -> List(Bool(true)),
// FLW -> List(Bool(true)),
// FLD -> List(Bool(true)),
// FSW -> List(Bool(true)),
// FSD -> List(Bool(true)),
// FMADD_S -> List(Bool(true)),
// FMSUB_S -> List(Bool(true)),
// FNMSUB_S -> List(Bool(true)),
// FNMADD_S -> List(Bool(true)),
// FMADD_D -> List(Bool(true)),
// FMSUB_D -> List(Bool(true)),
// FNMSUB_D -> List(Bool(true)),
// FNMADD_D -> List(Bool(true))
// ));
// val id_fp_val :: Nil = fp;
val fpdec = new rocketFPUDecoder
fpdec.io.inst := io.dpath.inst
val xpr64 = Y;
val cs =
@ -273,12 +211,12 @@ class rocketCtrl extends Component
// Instructions that have not yet been implemented
// Faking these for now so akaros will boot
MFFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
MTFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FLW-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FLD-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSW-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSD-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N)
//MFFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
//MTFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FLW-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FLD-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSW-> List(Y, BR_N, REN_N,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSD-> List(Y, BR_N, REN_N,REN_Y,A2_SPLIT,A1_RS1,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N)
/*
// floating point
FLW-> List(FPU_Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_FRD, MT_WU,N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
@ -293,6 +231,7 @@ class rocketCtrl extends Component
val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_sel_alu1 :: id_fn_dw :: id_fn_alu :: csremainder = cs;
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = csremainder;
val id_raddr3 = io.dpath.inst(16,12);
val id_raddr2 = io.dpath.inst(21,17);
val id_raddr1 = io.dpath.inst(26,22);
val id_waddr = Mux(id_sel_wa === WA_RA, RA, io.dpath.inst(31,27));
@ -300,23 +239,7 @@ class rocketCtrl extends Component
val id_console_out_val = id_wen_pcr.toBool && (id_raddr2 === PCR_CONSOLE);
val wb_reg_div_mul_val = Reg(resetVal = Bool(false))
val dcache_miss = Reg(io.dmem.resp_miss, resetVal = Bool(false));
val sboard = new rocketCtrlSboard();
sboard.io.raddra := id_raddr2.toUFix;
sboard.io.raddrb := id_raddr1.toUFix;
sboard.io.raddrc := id_waddr.toUFix;
// scoreboard set (for D$ misses, div, mul)
sboard.io.set := wb_reg_div_mul_val | dcache_miss;
sboard.io.seta := io.dpath.wb_waddr;
sboard.io.clr := io.dpath.sboard_clr;
sboard.io.clra := io.dpath.sboard_clra;
val id_stall_raddr2 = sboard.io.stalla;
val id_stall_raddr1 = sboard.io.stallb;
val id_stall_waddr = sboard.io.stallc;
val wb_reg_dcache_miss = Reg(io.dmem.resp_miss, resetVal = Bool(false));
val id_reg_btb_hit = Reg(resetVal = Bool(false));
val id_reg_xcpt_itlb = Reg(resetVal = Bool(false));
@ -332,6 +255,8 @@ class rocketCtrl extends Component
val ex_reg_mem_val = Reg(){Bool()};
val ex_reg_mem_cmd = Reg(){UFix(width = 4)};
val ex_reg_mem_type = Reg(){UFix(width = 3)};
val ex_reg_wen = Reg(resetVal = Bool(false));
val ex_reg_fp_wen = Reg(resetVal = Bool(false));
val ex_reg_eret = Reg(resetVal = Bool(false));
val ex_reg_replay_next = Reg(resetVal = Bool(false));
val ex_reg_inst_di = Reg(resetVal = Bool(false));
@ -341,11 +266,13 @@ class rocketCtrl extends Component
val ex_reg_xcpt_itlb = Reg(resetVal = Bool(false));
val ex_reg_xcpt_illegal = Reg(resetVal = Bool(false));
val ex_reg_xcpt_privileged = Reg(resetVal = Bool(false));
val ex_reg_xcpt_fpu = Reg(resetVal = Bool(false));
val ex_reg_xcpt_syscall = Reg(resetVal = Bool(false));
val ex_reg_fp_val = Reg(resetVal = Bool(false));
val ex_reg_replay = Reg(resetVal = Bool(false));
val ex_reg_load_use = Reg(resetVal = Bool(false));
val mem_reg_wen = Reg(resetVal = Bool(false));
val mem_reg_fp_wen = Reg(resetVal = Bool(false));
val mem_reg_inst_di = Reg(resetVal = Bool(false));
val mem_reg_inst_ei = Reg(resetVal = Bool(false));
val mem_reg_flush_inst = Reg(resetVal = Bool(false));
@ -358,6 +285,8 @@ class rocketCtrl extends Component
val mem_reg_replay = Reg(resetVal = Bool(false));
val mem_reg_kill = Reg(resetVal = Bool(false));
val wb_reg_wen = Reg(resetVal = Bool(false));
val wb_reg_fp_wen = Reg(resetVal = Bool(false));
val wb_reg_inst_di = Reg(resetVal = Bool(false));
val wb_reg_inst_ei = Reg(resetVal = Bool(false));
val wb_reg_flush_inst = Reg(resetVal = Bool(false));
@ -384,8 +313,7 @@ class rocketCtrl extends Component
}
// executing ERET when traps are enabled causes an illegal instruction exception (as per ISA sim)
// val illegal_inst = !(id_int_val.toBool || id_fp_val.toBool) || (id_eret.toBool && io.dpath.status(SR_ET).toBool);
val illegal_inst = !id_int_val.toBool || (id_eret.toBool && io.dpath.status(SR_ET).toBool);
val illegal_inst = !(id_int_val.toBool || fpdec.io.valid) || (id_eret.toBool && io.dpath.status(SR_ET).toBool);
when (reset.toBool || io.dpath.killd) {
ex_reg_br_type <== BR_N;
@ -393,6 +321,8 @@ class rocketCtrl extends Component
ex_reg_div_val <== Bool(false);
ex_reg_mul_val <== Bool(false);
ex_reg_mem_val <== Bool(false);
ex_reg_wen <== Bool(false);
ex_reg_fp_wen <== Bool(false);
ex_reg_eret <== Bool(false);
ex_reg_replay_next <== Bool(false);
ex_reg_inst_di <== Bool(false);
@ -402,8 +332,8 @@ class rocketCtrl extends Component
ex_reg_xcpt_itlb <== Bool(false);
ex_reg_xcpt_illegal <== Bool(false);
ex_reg_xcpt_privileged <== Bool(false);
ex_reg_xcpt_fpu <== Bool(false);
ex_reg_xcpt_syscall <== Bool(false);
ex_reg_fp_val <== Bool(false);
ex_reg_replay <== Bool(false);
ex_reg_load_use <== Bool(false);
}
@ -413,6 +343,8 @@ class rocketCtrl extends Component
ex_reg_div_val <== id_div_val.toBool;
ex_reg_mul_val <== id_mul_val.toBool;
ex_reg_mem_val <== id_mem_val.toBool;
ex_reg_wen <== id_wen.toBool;
ex_reg_fp_wen <== fpdec.io.wen;
ex_reg_eret <== id_eret.toBool;
ex_reg_replay_next <== id_replay_next.toBool;
ex_reg_inst_di <== (id_irq === I_DI);
@ -422,9 +354,8 @@ class rocketCtrl extends Component
ex_reg_xcpt_itlb <== id_reg_xcpt_itlb;
ex_reg_xcpt_illegal <== illegal_inst;
ex_reg_xcpt_privileged <== (id_privileged & ~io.dpath.status(SR_S)).toBool;
// ex_reg_xcpt_fpu <== id_fp_val.toBool;
ex_reg_xcpt_fpu <== Bool(false);
ex_reg_xcpt_syscall <== id_syscall.toBool;
ex_reg_fp_val <== fpdec.io.valid;
ex_reg_replay <== id_reg_replay || ex_reg_replay_next;
ex_reg_load_use <== id_load_use;
}
@ -461,6 +392,8 @@ class rocketCtrl extends Component
when (reset.toBool || io.dpath.killx) {
mem_reg_div_mul_val <== Bool(false);
mem_reg_wen <== Bool(false);
mem_reg_fp_wen <== Bool(false);
mem_reg_eret <== Bool(false);
mem_reg_mem_val <== Bool(false);
mem_reg_inst_di <== Bool(false);
@ -475,6 +408,8 @@ class rocketCtrl extends Component
}
otherwise {
mem_reg_div_mul_val <== ex_reg_div_val || ex_reg_mul_val;
mem_reg_wen <== ex_reg_wen;
mem_reg_fp_wen <== ex_reg_fp_wen;
mem_reg_eret <== ex_reg_eret;
mem_reg_mem_val <== ex_reg_mem_val;
mem_reg_inst_di <== ex_reg_inst_di;
@ -484,13 +419,15 @@ class rocketCtrl extends Component
mem_reg_xcpt_itlb <== ex_reg_xcpt_itlb;
mem_reg_xcpt_illegal <== ex_reg_xcpt_illegal;
mem_reg_xcpt_privileged <== ex_reg_xcpt_privileged;
mem_reg_xcpt_fpu <== ex_reg_xcpt_fpu;
mem_reg_xcpt_fpu <== ex_reg_fp_val && !io.dpath.status(SR_EF).toBool;
mem_reg_xcpt_syscall <== ex_reg_xcpt_syscall;
}
mem_reg_mem_cmd <== ex_reg_mem_cmd;
mem_reg_mem_type <== ex_reg_mem_type;
when (io.dpath.killm) {
wb_reg_wen <== Bool(false);
wb_reg_fp_wen <== Bool(false);
wb_reg_eret <== Bool(false);
wb_reg_inst_di <== Bool(false);
wb_reg_inst_ei <== Bool(false);
@ -498,6 +435,8 @@ class rocketCtrl extends Component
wb_reg_div_mul_val <== Bool(false);
}
otherwise {
wb_reg_wen <== mem_reg_wen;
wb_reg_fp_wen <== mem_reg_fp_wen;
wb_reg_eret <== mem_reg_eret;
wb_reg_inst_di <== mem_reg_inst_di;
wb_reg_inst_ei <== mem_reg_inst_ei;
@ -505,6 +444,42 @@ class rocketCtrl extends Component
wb_reg_div_mul_val <== mem_reg_div_mul_val;
}
val sboard = new rocketCtrlSboard();
sboard.io.raddra := id_raddr2.toUFix;
sboard.io.raddrb := id_raddr1.toUFix;
sboard.io.raddrc := id_waddr.toUFix;
// scoreboard set (for D$ misses, div, mul)
sboard.io.set := wb_reg_div_mul_val || wb_reg_dcache_miss && wb_reg_wen;
sboard.io.seta := io.dpath.wb_waddr;
sboard.io.clr := io.dpath.sboard_clr;
sboard.io.clra := io.dpath.sboard_clra;
val id_stall_raddr2 = id_renx2.toBool && sboard.io.stalla;
val id_stall_raddr1 = id_renx1.toBool && sboard.io.stallb;
val id_stall_waddr = id_wen.toBool && sboard.io.stallc;
var id_stall_fpu = Bool(false)
if (HAVE_FPU) {
val fp_sboard = new rocketCtrlSboard();
fp_sboard.io.raddra := id_raddr1.toUFix;
fp_sboard.io.raddrb := id_raddr2.toUFix;
fp_sboard.io.raddrc := id_raddr3.toUFix;
fp_sboard.io.raddrd := id_waddr.toUFix;
fp_sboard.io.set := wb_reg_dcache_miss && wb_reg_fp_wen;
fp_sboard.io.seta := io.dpath.wb_waddr;
fp_sboard.io.clr := io.dpath.fp_sboard_clr;
fp_sboard.io.clra := io.dpath.fp_sboard_clra;
id_stall_fpu = fpdec.io.ren1 && fp_sboard.io.stalla ||
fpdec.io.ren2 && fp_sboard.io.stallb ||
fpdec.io.ren3 && fp_sboard.io.stallc ||
fpdec.io.wen && fp_sboard.io.stalld
}
// exception handling
// FIXME: verify PC in MEM stage points to valid, restartable instruction
val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer);
@ -565,7 +540,7 @@ class rocketCtrl extends Component
// replay execute stage PC when the D$ is blocked, when the D$ misses,
// for privileged instructions, and for fence.i instructions
val replay_ex = dcache_miss && ex_reg_load_use || mem_reg_flush_inst ||
val replay_ex = wb_reg_dcache_miss && ex_reg_load_use || mem_reg_flush_inst ||
ex_reg_replay || ex_reg_mem_val && !(io.dmem.req_rdy && io.dtlb_rdy) ||
ex_reg_div_val && !io.dpath.div_rdy ||
ex_reg_mul_val && !io.dpath.mul_rdy
@ -601,57 +576,63 @@ class rocketCtrl extends Component
io.imem.req_val := take_pc_wb || !mem_reg_replay && !ex_reg_replay && (take_pc_ex || !id_reg_replay)
// stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage.
val ex_mem_cmd_load =
ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool);
val data_hazard_ex =
((id_renx1.toBool && (id_raddr1 === io.dpath.ex_waddr)) ||
(id_renx2.toBool && (id_raddr2 === io.dpath.ex_waddr)) ||
(id_wen.toBool && (id_waddr === io.dpath.ex_waddr)));
val id_ex_hazard = data_hazard_ex && (ex_mem_cmd_load || ex_reg_div_val || ex_reg_mul_val)
val data_hazard_ex = ex_reg_wen &&
(id_renx1.toBool && id_raddr1 === io.dpath.ex_waddr ||
id_renx2.toBool && id_raddr2 === io.dpath.ex_waddr ||
id_wen.toBool && id_waddr === io.dpath.ex_waddr)
val fp_data_hazard_ex = ex_reg_fp_wen &&
(fpdec.io.ren1 && id_raddr1 === io.dpath.ex_waddr ||
fpdec.io.ren2 && id_raddr2 === io.dpath.ex_waddr ||
fpdec.io.ren3 && id_raddr3 === io.dpath.ex_waddr ||
fpdec.io.wen && id_waddr === io.dpath.ex_waddr)
val id_ex_hazard = data_hazard_ex && (ex_reg_mem_val || ex_reg_div_val || ex_reg_mul_val) ||
fp_data_hazard_ex && ex_reg_mem_val
// stall for RAW/WAW hazards on LB/LH and mul/div in memory stage.
val mem_mem_cmd_load =
mem_reg_mem_val && ((mem_reg_mem_cmd === M_XRD) || mem_reg_mem_cmd(3).toBool);
val mem_mem_cmd_load_bh =
mem_mem_cmd_load &&
((mem_reg_mem_type === MT_B) ||
(mem_reg_mem_type === MT_BU) ||
(mem_reg_mem_type === MT_H) ||
(mem_reg_mem_type === MT_HU));
val data_hazard_mem =
(id_renx1.toBool && (id_raddr1 === io.dpath.mem_waddr)) ||
(id_renx2.toBool && (id_raddr2 === io.dpath.mem_waddr)) ||
(id_wen.toBool && (id_waddr === io.dpath.mem_waddr));
val id_mem_hazard = data_hazard_mem && (mem_mem_cmd_load_bh || mem_reg_div_mul_val)
id_load_use := mem_mem_cmd_load && data_hazard_mem
val mem_mem_cmd_bh =
(mem_reg_mem_type === MT_B) || (mem_reg_mem_type === MT_BU) ||
(mem_reg_mem_type === MT_H) || (mem_reg_mem_type === MT_HU)
val data_hazard_mem = mem_reg_wen &&
(id_renx1.toBool && id_raddr1 === io.dpath.mem_waddr ||
id_renx2.toBool && id_raddr2 === io.dpath.mem_waddr ||
id_wen.toBool && id_waddr === io.dpath.mem_waddr)
val fp_data_hazard_mem = mem_reg_fp_wen &&
(fpdec.io.ren1 && id_raddr1 === io.dpath.mem_waddr ||
fpdec.io.ren2 && id_raddr2 === io.dpath.mem_waddr ||
fpdec.io.ren3 && id_raddr3 === io.dpath.mem_waddr ||
fpdec.io.wen && id_waddr === io.dpath.mem_waddr)
val id_mem_hazard = data_hazard_mem && (mem_mem_cmd_bh || mem_reg_div_mul_val)
id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem)
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
val data_hazard_wb =
((id_renx1.toBool && (id_raddr1 === io.dpath.wb_waddr)) ||
(id_renx2.toBool && (id_raddr2 === io.dpath.wb_waddr)) ||
(id_wen.toBool && (id_waddr === io.dpath.wb_waddr)));
val id_wb_hazard = data_hazard_wb && (dcache_miss || wb_reg_div_mul_val)
val data_hazard_wb = wb_reg_wen &&
(id_renx1.toBool && id_raddr1 === io.dpath.wb_waddr ||
id_renx2.toBool && id_raddr2 === io.dpath.wb_waddr ||
id_wen.toBool && id_waddr === io.dpath.wb_waddr)
val fp_data_hazard_wb = wb_reg_fp_wen &&
(fpdec.io.ren1 && id_raddr1 === io.dpath.wb_waddr ||
fpdec.io.ren2 && id_raddr2 === io.dpath.wb_waddr ||
fpdec.io.ren3 && id_raddr3 === io.dpath.wb_waddr ||
fpdec.io.wen && id_waddr === io.dpath.wb_waddr)
val id_wb_hazard = data_hazard_wb && (wb_reg_dcache_miss || wb_reg_div_mul_val) ||
fp_data_hazard_wb && wb_reg_dcache_miss
// for divider, multiplier, load miss writeback
val mem_wb = Reg(io.dmem.resp_replay, resetVal = Bool(false)) // delayed for subword extension
val mul_wb = io.dpath.mul_result_val && !mem_wb;
val div_wb = io.dpath.div_result_val && !io.dpath.mul_result_val && !mem_wb;
val mul_wb = io.dpath.mul_result_val && !io.dpath.mem_wb;
val div_wb = io.dpath.div_result_val && !io.dpath.mul_result_val && !io.dpath.mem_wb;
val ctrl_stalld =
!take_pc &&
(
id_ex_hazard || id_mem_hazard || id_wb_hazard ||
id_renx2.toBool && id_stall_raddr2 ||
id_renx1.toBool && id_stall_raddr1 ||
id_wen.toBool && id_stall_waddr ||
id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr ||
id_stall_fpu ||
id_mem_val.toBool && !(io.dmem.req_rdy && io.dtlb_rdy) ||
((id_sync === SYNC_D) || (id_sync === SYNC_I)) && !io.dmem.req_rdy ||
id_console_out_val && !io.console.rdy ||
id_div_val.toBool && (!io.dpath.div_rdy || ex_reg_div_val) ||
id_mul_val.toBool && (!io.dpath.mul_rdy || ex_reg_mul_val) ||
io.dpath.div_result_val ||
io.dpath.mul_result_val ||
mem_wb
io.dpath.mem_wb
);
val ctrl_stallf = ctrl_stalld;
@ -668,7 +649,7 @@ class rocketCtrl extends Component
io.dpath.killx := kill_ex;
io.dpath.killm := kill_mem;
io.dpath.mem_load := mem_reg_mem_val && ((mem_reg_mem_cmd === M_XRD) || mem_reg_mem_cmd(3).toBool);
io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen
io.dpath.ren2 := id_renx2.toBool;
io.dpath.ren1 := id_renx1.toBool;
io.dpath.sel_alu2 := id_sel_alu2;
@ -681,7 +662,10 @@ class rocketCtrl extends Component
io.dpath.mul_fn := id_mul_fn;
io.dpath.mul_val := id_mul_val.toBool;
io.dpath.mul_wb := mul_wb;
io.dpath.wen := id_wen.toBool;
io.dpath.ex_fp_val:= ex_reg_fp_val;
io.dpath.ex_wen := ex_reg_wen;
io.dpath.mem_wen := mem_reg_wen;
io.dpath.wb_wen := wb_reg_wen;
io.dpath.sel_wa := id_sel_wa.toBool;
io.dpath.sel_wb := id_sel_wb;
io.dpath.ren_pcr := id_ren_pcr.toBool;

3
rocket/src/main/scala/ctrl_util.scala
View File

@ -13,9 +13,11 @@ class ioCtrlSboard extends Bundle()
val raddra = UFix(5, INPUT);
val raddrb = UFix(5, INPUT);
val raddrc = UFix(5, INPUT);
val raddrd = UFix(5, INPUT);
val stalla = Bool(OUTPUT);
val stallb = Bool(OUTPUT);
val stallc = Bool(OUTPUT);
val stalld = Bool(OUTPUT);
}
class rocketCtrlSboard extends Component
@ -30,6 +32,7 @@ class rocketCtrlSboard extends Component
io.stalla := reg_busy(io.raddra).toBool;
io.stallb := reg_busy(io.raddrb).toBool;
io.stallc := reg_busy(io.raddrc).toBool;
io.stalld := reg_busy(io.raddrd).toBool;
}
class ioCtrlCnt extends Bundle()

46
rocket/src/main/scala/dpath.scala
View File

@ -34,6 +34,7 @@ class ioDpathAll extends Bundle()
val imem = new ioDpathImem();
val ptbr_wen = Bool(OUTPUT);
val ptbr = UFix(PADDR_BITS, OUTPUT);
val fpu = new ioDpathFPU();
}
class rocketDpath extends Component
@ -90,7 +91,6 @@ class rocketDpath extends Component
val ex_reg_ctrl_div_val = Reg(resetVal = Bool(false));
val ex_reg_ctrl_div_fn = Reg() { UFix() };
val ex_reg_ctrl_sel_wb = Reg() { UFix() };
val ex_reg_ctrl_wen = Reg(resetVal = Bool(false));
val ex_reg_ctrl_ren_pcr = Reg(resetVal = Bool(false));
val ex_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
val ex_wdata = Wire() { Bits() };
@ -104,7 +104,6 @@ class rocketDpath extends Component
val mem_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
val mem_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
val mem_reg_ctrl_div_val = Reg(resetVal = Bool(false));
val mem_reg_ctrl_wen = Reg(resetVal = Bool(false));
val mem_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
val mem_wdata = Wire() { Bits() };
@ -115,12 +114,11 @@ class rocketDpath extends Component
val wb_reg_wdata = Reg() { Bits() };
val wb_reg_raddr2 = Reg() { UFix() };
val wb_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
val wb_reg_ctrl_wen = Reg(resetVal = Bool(false));
val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
val wb_wdata = Wire() { Bits() };
val r_dmem_resp_val = Reg(resetVal = Bool(false));
val r_dmem_resp_replay = Reg(resetVal = Bool(false));
val r_dmem_fp_replay = Reg(resetVal = Bool(false));
val r_dmem_resp_waddr = Reg() { UFix() };
// instruction fetch stage
@ -210,15 +208,15 @@ class rocketDpath extends Component
Mux(r_dmem_resp_replay, io.dmem.resp_data_subword,
Mux(io.ctrl.div_wb, div_result,
Mux(io.ctrl.mul_wb, mul_result,
Mux(id_raddr1 != UFix(0, 5) && (ex_reg_ctrl_wen || ex_reg_ctrl_ll_wb) && id_raddr1 === ex_reg_waddr, ex_wdata,
Mux(id_raddr1 != UFix(0, 5) && (mem_reg_ctrl_wen || mem_reg_ctrl_ll_wb) && id_raddr1 === mem_reg_waddr, mem_wdata,
Mux(id_raddr1 != UFix(0, 5) && (wb_reg_ctrl_wen || wb_reg_ctrl_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata,
Mux(id_raddr1 != UFix(0, 5) && (io.ctrl.ex_wen || ex_reg_ctrl_ll_wb) && id_raddr1 === ex_reg_waddr, ex_wdata,
Mux(id_raddr1 != UFix(0, 5) && (io.ctrl.mem_wen || mem_reg_ctrl_ll_wb) && id_raddr1 === mem_reg_waddr, mem_wdata,
Mux(id_raddr1 != UFix(0, 5) && (io.ctrl.wb_wen || wb_reg_ctrl_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata,
id_rdata1))))));
val id_rs2 =
Mux(id_raddr2 != UFix(0, 5) && (ex_reg_ctrl_wen || ex_reg_ctrl_ll_wb) && id_raddr2 === ex_reg_waddr, ex_wdata,
Mux(id_raddr2 != UFix(0, 5) && (mem_reg_ctrl_wen || mem_reg_ctrl_ll_wb) && id_raddr2 === mem_reg_waddr, mem_wdata,
Mux(id_raddr2 != UFix(0, 5) && (wb_reg_ctrl_wen || wb_reg_ctrl_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
Mux(id_raddr2 != UFix(0, 5) && (io.ctrl.ex_wen || ex_reg_ctrl_ll_wb) && id_raddr2 === ex_reg_waddr, ex_wdata,
Mux(id_raddr2 != UFix(0, 5) && (io.ctrl.mem_wen || mem_reg_ctrl_ll_wb) && id_raddr2 === mem_reg_waddr, mem_wdata,
Mux(id_raddr2 != UFix(0, 5) && (io.ctrl.wb_wen || wb_reg_ctrl_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
id_rdata2)));
io.ctrl.inst := id_reg_inst;
@ -244,7 +242,6 @@ class rocketDpath extends Component
ex_reg_valid <== Bool(false);
ex_reg_ctrl_div_val <== Bool(false);
ex_reg_ctrl_mul_val <== Bool(false);
ex_reg_ctrl_wen <== Bool(false);
ex_reg_ctrl_wen_pcr <== Bool(false);
ex_reg_ctrl_eret <== Bool(false);
}
@ -252,7 +249,6 @@ class rocketDpath extends Component
ex_reg_valid <== id_reg_valid;
ex_reg_ctrl_div_val <== io.ctrl.div_val;
ex_reg_ctrl_mul_val <== io.ctrl.mul_val;
ex_reg_ctrl_wen <== io.ctrl.wen;
ex_reg_ctrl_wen_pcr <== io.ctrl.wen_pcr;
ex_reg_ctrl_eret <== io.ctrl.id_eret;
}
@ -307,8 +303,14 @@ class rocketDpath extends Component
// D$ request interface (registered inside D$ module)
// other signals (req_val, req_rdy) connect to control module
io.dmem.req_addr := ex_jr_target_extended.toUFix;
io.dmem.req_data := ex_reg_rs2;
io.dmem.req_tag := ex_reg_waddr;
if (HAVE_FPU) {
io.dmem.req_data := Mux(io.ctrl.ex_fp_val, io.fpu.store_data, ex_reg_rs2)
io.dmem.req_tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val).toUFix
}
else {
io.dmem.req_data := ex_reg_rs2
io.dmem.req_tag := Cat(ex_reg_waddr, Bool(false)).toUFix
}
// processor control regfile read
pcr.io.r.en := ex_reg_ctrl_ren_pcr | ex_reg_ctrl_eret;
@ -361,12 +363,10 @@ class rocketDpath extends Component
when (io.ctrl.killx) {
mem_reg_valid <== Bool(false);
mem_reg_ctrl_wen <== Bool(false);
mem_reg_ctrl_wen_pcr <== Bool(false);
}
otherwise {
mem_reg_valid <== ex_reg_valid;
mem_reg_ctrl_wen <== ex_reg_ctrl_wen;
mem_reg_ctrl_wen_pcr <== ex_reg_ctrl_wen_pcr;
}
@ -379,9 +379,10 @@ class rocketDpath extends Component
// 32/64 bit load handling (moved to earlier in file)
// writeback stage
r_dmem_resp_val <== io.dmem.resp_val;
r_dmem_resp_replay <== io.dmem.resp_replay;
r_dmem_resp_waddr <== io.dmem.resp_tag.toUFix
val dmem_resp_fpu = if (HAVE_FPU) io.dmem.resp_tag(0).toBool else Bool(false)
r_dmem_resp_replay <== io.dmem.resp_replay && !dmem_resp_fpu;
r_dmem_fp_replay <== io.dmem.resp_replay && dmem_resp_fpu;
r_dmem_resp_waddr <== io.dmem.resp_tag.toUFix >> UFix(1)
wb_reg_pc <== mem_reg_pc;
wb_reg_waddr <== mem_reg_waddr;
@ -391,26 +392,27 @@ class rocketDpath extends Component
when (io.ctrl.killm) {
wb_reg_valid <== Bool(false);
wb_reg_ctrl_wen <== Bool(false);
wb_reg_ctrl_wen_pcr <== Bool(false);
}
otherwise {
wb_reg_valid <== mem_reg_valid;
wb_reg_ctrl_wen <== mem_reg_ctrl_wen && !io.dmem.resp_miss;
wb_reg_ctrl_wen_pcr <== mem_reg_ctrl_wen_pcr;
}
// regfile write
wb_wdata := Mux(Reg(io.ctrl.mem_load), io.dmem.resp_data_subword, wb_reg_wdata)
rfile.io.w0.addr := wb_reg_waddr;
rfile.io.w0.en := wb_reg_ctrl_wen || wb_reg_ctrl_ll_wb;
rfile.io.w0.en := io.ctrl.wb_wen || wb_reg_ctrl_ll_wb;
rfile.io.w0.data := wb_wdata
io.ctrl.wb_waddr := wb_reg_waddr;
io.ctrl.mem_wb := r_dmem_resp_replay;
// scoreboard clear (for div/mul and D$ load miss writebacks)
io.ctrl.sboard_clr := id_ctrl_ll_wb;
io.ctrl.sboard_clra := id_waddr;
io.ctrl.fp_sboard_clr := r_dmem_fp_replay;
io.ctrl.fp_sboard_clra := r_dmem_resp_waddr;
// processor control regfile write
pcr.io.w.addr := wb_reg_raddr2;

6
rocket/src/main/scala/dpath_util.scala
View File

@ -159,9 +159,9 @@ class rocketDpathPCR extends Component
reg_status_ux <== io.w.data(SR_UX).toBool;
reg_status_s <== io.w.data(SR_S).toBool;
reg_status_ps <== io.w.data(SR_PS).toBool;
reg_status_ev <== HAVE_VEC && io.w.data(SR_EV).toBool;
reg_status_ef <== HAVE_FPU && io.w.data(SR_EF).toBool;
reg_status_ec <== HAVE_RVC && io.w.data(SR_EC).toBool;
reg_status_ev <== Bool(HAVE_VEC) && io.w.data(SR_EV).toBool;
reg_status_ef <== Bool(HAVE_FPU) && io.w.data(SR_EF).toBool;
reg_status_ec <== Bool(HAVE_RVC) && io.w.data(SR_EC).toBool;
reg_status_et <== io.w.data(SR_ET).toBool;
}
when (io.w.addr === PCR_EPC) { reg_epc <== io.w.data(VADDR_BITS,0).toUFix; }

148
rocket/src/main/scala/fpu.scala Normal file
View File

@ -0,0 +1,148 @@
package Top
import Chisel._
import Node._;
import Constants._
import Instructions._
class rocketFPUDecoder extends Component
{
val io = new Bundle {
val inst = Bits(32, INPUT)
val valid = Bool(OUTPUT)
val wen = Bool(OUTPUT)
val ren1 = Bool(OUTPUT)
val ren2 = Bool(OUTPUT)
val ren3 = Bool(OUTPUT)
}
// val fp =
// ListLookup(io.dpath.inst,
// List(FPU_N, FPU_N, FPU_N, FPU_N, FPU_N),
// Array(
// FMOVZ -> List(Bool(true)),
// FMOVN -> List(Bool(true)),
// FADD_S -> List(Bool(true)),
// FSUB_S -> List(Bool(true)),
// FMUL_S -> List(Bool(true)),
// FDIV_S -> List(Bool(true)),
// FSQRT_S -> List(Bool(true)),
// FSGNJ_S -> List(Bool(true)),
// FSGNJN_S -> List(Bool(true)),
// FSGNJX_S -> List(Bool(true)),
// FADD_D -> List(Bool(true)),
// FSUB_D -> List(Bool(true)),
// FMUL_D -> List(Bool(true)),
// FDIV_D -> List(Bool(true)),
// FSQRT_D -> List(Bool(true)),
// FSGNJ_D -> List(Bool(true)),
// FSGNJN_D -> List(Bool(true)),
// FSGNJX_D -> List(Bool(true)),
// FCVT_L_S -> List(Bool(true)),
// FCVT_LU_S -> List(Bool(true)),
// FCVT_W_S -> List(Bool(true)),
// FCVT_WU_S -> List(Bool(true)),
// FCVT_L_D -> List(Bool(true)),
// FCVT_LU_D -> List(Bool(true)),
// FCVT_W_D -> List(Bool(true)),
// FCVT_WU_D -> List(Bool(true)),
// FCVT_S_L -> List(Bool(true)),
// FCVT_S_LU -> List(Bool(true)),
// FCVT_S_W -> List(Bool(true)),
// FCVT_S_WU -> List(Bool(true)),
// FCVT_D_L -> List(Bool(true)),
// FCVT_D_LU -> List(Bool(true)),
// FCVT_D_W -> List(Bool(true)),
// FCVT_D_WU -> List(Bool(true)),
// FCVT_S_D -> List(Bool(true)),
// FCVT_D_S -> List(Bool(true)),
// FEQ_S -> List(Bool(true)),
// FLT_S -> List(Bool(true)),
// FLE_S -> List(Bool(true)),
// FEQ_D -> List(Bool(true)),
// FLT_D -> List(Bool(true)),
// FLE_D -> List(Bool(true)),
// FMIN_S -> List(Bool(true)),
// FMAX_S -> List(Bool(true)),
// FMIN_D -> List(Bool(true)),
// FMAX_D -> List(Bool(true)),
// MFTX_S -> List(Bool(true)),
// MFTX_D -> List(Bool(true)),
// MFFSR -> List(Bool(true)),
// MXTF_S -> List(Bool(true)),
// MXTF_D -> List(Bool(true)),
// MTFSR -> List(Bool(true)),
// FLW -> List(FPU_Y, FPU_Y, FPU_N, FPU_N, FPU_N),
// FLD -> List(FPU_Y, FPU_Y, FPU_N, FPU_N, FPU_N),
// FSW -> List(FPU_Y, FPU_N, FPU_N, FPU_Y, FPU_N),
// FSD -> List(FPU_Y, FPU_N, FPU_N, FPU_Y, FPU_N)
// FMADD_S -> List(Bool(true)),
// FMSUB_S -> List(Bool(true)),
// FNMSUB_S -> List(Bool(true)),
// FNMADD_S -> List(Bool(true)),
// FMADD_D -> List(Bool(true)),
// FMSUB_D -> List(Bool(true)),
// FNMSUB_D -> List(Bool(true)),
// FNMADD_D -> List(Bool(true))
// ));
val N = Bool(false)
val Y = Bool(true)
val decoder = ListLookup(io.inst,
List (N, N, N, N, N),
Array(FLW -> List(Y, Y, N, N, N),
FLD -> List(Y, Y, N, N, N),
FSW -> List(Y, N, N, Y, N),
FSD -> List(Y, N, N, Y, N)))
val valid :: wen :: ren1 :: ren2 :: ren3 :: Nil = decoder
io.valid := valid.toBool
io.wen := wen.toBool
io.ren1 := ren1.toBool
io.ren2 := ren2.toBool
io.ren3 := ren3.toBool
}
class ioDpathFPU extends Bundle {
val store_data = Bits(64, INPUT)
}
class rocketFPU extends Component
{
val io = new Bundle {
val req_valid = Bool(INPUT)
val req_ready = Bool(OUTPUT)
val req_cmd = Bits(6, INPUT)
val req_inst = Bits(32, INPUT)
val killx = Bool(INPUT)
val killm = Bool(INPUT)
val dmem = new ioDmem(List("resp_val", "resp_tag", "resp_data"))
val dpath = new ioDpathFPU().flip()
}
val ex_reg_inst = Reg() { Bits() }
when (io.req_valid) {
ex_reg_inst <== io.req_inst
}
// load response
val dmem_resp_val_fpu = io.dmem.resp_val && io.dmem.resp_tag(0).toBool
val load_wb = Reg(dmem_resp_val_fpu, resetVal = Bool(false))
val load_wb_data = Reg() { Bits() }
val load_wb_tag = Reg() { UFix() }
when (dmem_resp_val_fpu) {
load_wb_data <== io.dmem.resp_data
load_wb_tag <== io.dmem.resp_tag.toUFix >> UFix(1)
}
// regfile
val regfile = Mem4(32, load_wb_data);
regfile.setReadLatency(0);
regfile.setTarget('inst);
regfile.write(load_wb_tag, load_wb_data, load_wb);
io.req_ready := Bool(true)
io.dpath.store_data := regfile(ex_reg_inst(21,17))
}