61 lines
1.5 KiB
Scala
61 lines
1.5 KiB
Scala
package Top
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{
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import Chisel._
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import Node._;
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import Constants._;
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class ioCtrlSboard extends Bundle()
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{
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val clr = Bool(INPUT);
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val clra = UFix(5, INPUT);
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val set = Bool(INPUT);
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val seta = UFix(5, INPUT);
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val raddra = UFix(5, INPUT);
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val raddrb = UFix(5, INPUT);
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val raddrc = UFix(5, INPUT);
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val raddrd = UFix(5, INPUT);
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val stalla = Bool(OUTPUT);
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val stallb = Bool(OUTPUT);
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val stallc = Bool(OUTPUT);
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val stalld = Bool(OUTPUT);
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}
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class rocketCtrlSboard extends Component
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{
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override val io = new ioCtrlSboard();
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val reg_busy = Reg(width = 32, resetVal = Bits(0, 32));
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val set_mask = io.set.toUFix << io.seta;
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val clr_mask = ~(io.clr.toUFix << io.clra);
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reg_busy <== (reg_busy | set_mask) & clr_mask
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io.stalla := reg_busy(io.raddra).toBool;
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io.stallb := reg_busy(io.raddrb).toBool;
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io.stallc := reg_busy(io.raddrc).toBool;
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io.stalld := reg_busy(io.raddrd).toBool;
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}
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class ioCtrlCnt extends Bundle()
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{
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val enq = Bool(INPUT);
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val deq = Bool(INPUT);
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val empty = Bool(OUTPUT);
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val full = Bool(OUTPUT);
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}
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class rocketCtrlCnt(n_bits: Int, limit: Int) extends Component
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{
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override val io = new ioCtrlCnt();
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val counter = Reg(width = n_bits, resetVal = UFix(0, n_bits));
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when (io.enq && !io.deq) {
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counter <== counter + UFix(1, n_bits);
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}
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when (!io.enq && io.deq) {
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counter <== counter - UFix(1, n_bits);
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}
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io.empty := counter === UFix(0, n_bits);
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io.full := counter === UFix(limit, n_bits);
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}
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}
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