From 53f726008bf80761006208b0e53b02c476c43a28 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 24 Nov 2013 14:16:53 -0800 Subject: [PATCH] Use Mem instead of Vec[Reg] for TLB QoR-neutral, improves simulation speed --- rocket/src/main/scala/tlb.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala index 45d5078a..cb999ed0 100644 --- a/rocket/src/main/scala/tlb.scala +++ b/rocket/src/main/scala/tlb.scala @@ -20,7 +20,7 @@ class CAMIO(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle { class RocketCAM(entries: Int, tag_bits: Int) extends Module { val addr_bits = ceil(log(entries)/log(2)).toInt; val io = new CAMIO(entries, addr_bits, tag_bits); - val cam_tags = Vec.fill(entries){Reg(Bits(width = tag_bits))} + val cam_tags = Mem(Bits(width = tag_bits), entries) val vb_array = Reg(init=Bits(0, entries)) when (io.write) {