riscv/rocket-chip
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fix long-standing dcache bug

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have to initialize register, if it is used the same cycle it is begin written
This commit is contained in:
Yunsup Lee 2015-03-17 21:45:17 -07:00
parent 5b4653b621
commit 53617d6df5
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -628,7 +628,7 @@ class HellaCache extends L1HellaCacheModule {
val s3_req = Reg(io.cpu.req.bits.clone) val s3_req = Reg(io.cpu.req.bits.clone)
val s3_way = Reg(Bits()) val s3_way = Reg(Bits())
val s1_recycled = RegEnable(s2_recycle, s1_clk_en) val s1_recycled = RegEnable(s2_recycle, Bool(false), s1_clk_en)
val s1_read = isRead(s1_req.cmd) val s1_read = isRead(s1_req.cmd)
val s1_write = isWrite(s1_req.cmd) val s1_write = isWrite(s1_req.cmd)
val s1_sc = s1_req.cmd === M_XSC val s1_sc = s1_req.cmd === M_XSC