From 53617d6df58402f32221f4345acafc1a7fd571f3 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 17 Mar 2015 21:45:17 -0700 Subject: [PATCH] fix long-standing dcache bug have to initialize register, if it is used the same cycle it is begin written --- rocket/src/main/scala/nbdcache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 7d124d92..3f24ba4c 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -628,7 +628,7 @@ class HellaCache extends L1HellaCacheModule { val s3_req = Reg(io.cpu.req.bits.clone) val s3_way = Reg(Bits()) - val s1_recycled = RegEnable(s2_recycle, s1_clk_en) + val s1_recycled = RegEnable(s2_recycle, Bool(false), s1_clk_en) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_sc = s1_req.cmd === M_XSC