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Change SystemVerilog statement into standard Verilog (#997)

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pbing 2017-09-18 19:57:07 +02:00 committed by Andrew Waterman
parent c24b275fd9
commit 528deefdc7
1 changed files with 1 additions and 1 deletions
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scripts/vlsi_rom_gen
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@ -30,7 +30,7 @@ module {name}(
initial begin
`ifdef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
for (i = 0; i < {depth}; i++) begin
for (i = 0; i < {depth}; i = i + 1) begin
rom[i] = {{{num_random_blocks}{{$random}}}};
end
`endif