From 528deefdc754444e76146c896dc20d4edfffde9f Mon Sep 17 00:00:00 2001
From: pbing <bernd.beuster@gmail.com>
Date: Mon, 18 Sep 2017 19:57:07 +0200
Subject: [PATCH] Change SystemVerilog statement into standard Verilog (#997)

---
 scripts/vlsi_rom_gen | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/vlsi_rom_gen b/scripts/vlsi_rom_gen
index a6539725..3e97070d 100755
--- a/scripts/vlsi_rom_gen
+++ b/scripts/vlsi_rom_gen
@@ -30,7 +30,7 @@ module {name}(
   initial begin
 `ifdef RANDOMIZE
   `ifdef RANDOMIZE_MEM_INIT
-    for (i = 0; i < {depth}; i++) begin
+    for (i = 0; i < {depth}; i = i + 1) begin
       rom[i] = {{{num_random_blocks}{{$random}}}};
     end
   `endif