diff --git a/src/main/scala/coreplex/Ports.scala b/src/main/scala/coreplex/Ports.scala
index 90092e4b..438e0d1e 100644
--- a/src/main/scala/coreplex/Ports.scala
+++ b/src/main/scala/coreplex/Ports.scala
@@ -195,7 +195,7 @@ trait HasMasterTLMMIOPortBundle {
 trait HasMasterTLMMIOPortModuleImp extends LazyModuleImp with HasMasterTLMMIOPortBundle {
   val outer: HasMasterTLMMIOPort
   val mmio_tl = IO(HeterogeneousBag.fromNode(outer.mmio_tl.in))
-  (mmio_tl zip outer.mmio_tl.out) foreach { case (i, (o, _)) => i <> o }
+  (mmio_tl zip outer.mmio_tl.in) foreach { case (i, (o, _)) => i <> o }
 }
 
 /** Adds an TL port to the system intended to be a slave on an MMIO device bus.