From f749e986cfcf5bfacfc6165c050f77fd441fbc8d Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 5 Jan 2018 12:27:18 +0100 Subject: [PATCH] coreplex: fix TL MMIO port example --- src/main/scala/coreplex/Ports.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/Ports.scala b/src/main/scala/coreplex/Ports.scala index 90092e4b..438e0d1e 100644 --- a/src/main/scala/coreplex/Ports.scala +++ b/src/main/scala/coreplex/Ports.scala @@ -195,7 +195,7 @@ trait HasMasterTLMMIOPortBundle { trait HasMasterTLMMIOPortModuleImp extends LazyModuleImp with HasMasterTLMMIOPortBundle { val outer: HasMasterTLMMIOPort val mmio_tl = IO(HeterogeneousBag.fromNode(outer.mmio_tl.in)) - (mmio_tl zip outer.mmio_tl.out) foreach { case (i, (o, _)) => i <> o } + (mmio_tl zip outer.mmio_tl.in) foreach { case (i, (o, _)) => i <> o } } /** Adds an TL port to the system intended to be a slave on an MMIO device bus.